--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef _SAME70Q21_\r
+#define _SAME70Q21_\r
+\r
+/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions\r
+ This file defines all structures and symbols for SAME70Q21:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< 3 HardFault Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */\r
+/****** SAME70Q21 specific Interrupt Numbers *********************************/\r
+ \r
+ SUPC_IRQn = 0, /**< 0 SAME70Q21 Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAME70Q21 Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAME70Q21 Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAME70Q21 Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAME70Q21 Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAME70Q21 Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 7, /**< 7 SAME70Q21 UART 0 (UART0) */\r
+ UART1_IRQn = 8, /**< 8 SAME70Q21 UART 1 (UART1) */\r
+ PIOA_IRQn = 10, /**< 10 SAME70Q21 Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 11, /**< 11 SAME70Q21 Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 12, /**< 12 SAME70Q21 Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 13, /**< 13 SAME70Q21 USART 0 (USART0) */\r
+ USART1_IRQn = 14, /**< 14 SAME70Q21 USART 1 (USART1) */\r
+ USART2_IRQn = 15, /**< 15 SAME70Q21 USART 2 (USART2) */\r
+ PIOD_IRQn = 16, /**< 16 SAME70Q21 Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 17, /**< 17 SAME70Q21 Parallel I/O Controller E (PIOE) */\r
+ HSMCI_IRQn = 18, /**< 18 SAME70Q21 Multimedia Card Interface (HSMCI) */\r
+ TWIHS0_IRQn = 19, /**< 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */\r
+ TWIHS1_IRQn = 20, /**< 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */\r
+ SPI0_IRQn = 21, /**< 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */\r
+ SSC_IRQn = 22, /**< 22 SAME70Q21 Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAME70Q21 Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAME70Q21 Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAME70Q21 Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAME70Q21 Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAME70Q21 Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAME70Q21 Timer/Counter 5 (TC5) */\r
+ AFEC0_IRQn = 29, /**< 29 SAME70Q21 Analog Front End 0 (AFEC0) */\r
+ DACC_IRQn = 30, /**< 30 SAME70Q21 Digital To Analog Converter (DACC) */\r
+ PWM0_IRQn = 31, /**< 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */\r
+ ICM_IRQn = 32, /**< 32 SAME70Q21 Integrity Check Monitor (ICM) */\r
+ ACC_IRQn = 33, /**< 33 SAME70Q21 Analog Comparator (ACC) */\r
+ USBHS_IRQn = 34, /**< 34 SAME70Q21 USB Host / Device Controller (USBHS) */\r
+ MCAN0_IRQn = 35, /**< 35 SAME70Q21 MCAN Controller 0 (MCAN0) */\r
+ MCAN1_IRQn = 37, /**< 37 SAME70Q21 MCAN Controller 1 (MCAN1) */\r
+ GMAC_IRQn = 39, /**< 39 SAME70Q21 Ethernet MAC (GMAC) */\r
+ AFEC1_IRQn = 40, /**< 40 SAME70Q21 Analog Front End 1 (AFEC1) */\r
+ TWIHS2_IRQn = 41, /**< 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */\r
+ SPI1_IRQn = 42, /**< 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */\r
+ QSPI_IRQn = 43, /**< 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */\r
+ UART2_IRQn = 44, /**< 44 SAME70Q21 UART 2 (UART2) */\r
+ UART3_IRQn = 45, /**< 45 SAME70Q21 UART 3 (UART3) */\r
+ UART4_IRQn = 46, /**< 46 SAME70Q21 UART 4 (UART4) */\r
+ TC6_IRQn = 47, /**< 47 SAME70Q21 Timer/Counter 6 (TC6) */\r
+ TC7_IRQn = 48, /**< 48 SAME70Q21 Timer/Counter 7 (TC7) */\r
+ TC8_IRQn = 49, /**< 49 SAME70Q21 Timer/Counter 8 (TC8) */\r
+ TC9_IRQn = 50, /**< 50 SAME70Q21 Timer/Counter 9 (TC9) */\r
+ TC10_IRQn = 51, /**< 51 SAME70Q21 Timer/Counter 10 (TC10) */\r
+ TC11_IRQn = 52, /**< 52 SAME70Q21 Timer/Counter 11 (TC11) */\r
+ AES_IRQn = 56, /**< 56 SAME70Q21 AES (AES) */\r
+ TRNG_IRQn = 57, /**< 57 SAME70Q21 True Random Generator (TRNG) */\r
+ XDMAC_IRQn = 58, /**< 58 SAME70Q21 DMA (XDMAC) */\r
+ ISI_IRQn = 59, /**< 59 SAME70Q21 Camera Interface (ISI) */\r
+ PWM1_IRQn = 60, /**< 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */\r
+ SDRAMC_IRQn = 62, /**< 62 SAME70Q21 SDRAM Controller (SDRAMC) */\r
+ RSWDT_IRQn = 63, /**< 63 SAME70Q21 Reinforced Secure Watchdog Timer (RSWDT) */\r
+\r
+ PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+ \r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pfnUART0_Handler; /* 7 UART 0 */\r
+ void* pfnUART1_Handler; /* 8 UART 1 */\r
+ void* pvReserved9;\r
+ void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 13 USART 0 */\r
+ void* pfnUSART1_Handler; /* 14 USART 1 */\r
+ void* pfnUSART2_Handler; /* 15 USART 2 */\r
+ void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */\r
+ void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */\r
+ void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */\r
+ void* pfnICM_Handler; /* 32 Integrity Check Monitor */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */\r
+ void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */\r
+ void* pvReserved36;\r
+ void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */\r
+ void* pvReserved38;\r
+ void* pfnGMAC_Handler; /* 39 Ethernet MAC */\r
+ void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */\r
+ void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */\r
+ void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */\r
+ void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */\r
+ void* pfnUART2_Handler; /* 44 UART 2 */\r
+ void* pfnUART3_Handler; /* 45 UART 3 */\r
+ void* pfnUART4_Handler; /* 46 UART 4 */\r
+ void* pfnTC6_Handler; /* 47 Timer/Counter 6 */\r
+ void* pfnTC7_Handler; /* 48 Timer/Counter 7 */\r
+ void* pfnTC8_Handler; /* 49 Timer/Counter 8 */\r
+ void* pfnTC9_Handler; /* 50 Timer/Counter 9 */\r
+ void* pfnTC10_Handler; /* 51 Timer/Counter 10 */\r
+ void* pfnTC11_Handler; /* 52 Timer/Counter 11 */\r
+ void* pvReserved53;\r
+ void* pvReserved54;\r
+ void* pvReserved55;\r
+ void* pfnAES_Handler; /* 56 AES */\r
+ void* pfnTRNG_Handler; /* 57 True Random Generator */\r
+ void* pfnXDMAC_Handler; /* 58 DMA */\r
+ void* pfnISI_Handler; /* 59 Camera Interface */\r
+ void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */\r
+ void* pvReserved61;\r
+ void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */\r
+ void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M7 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void AES_Handler ( void );\r
+void AFEC0_Handler ( void );\r
+void AFEC1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void GMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void ICM_Handler ( void );\r
+void ISI_Handler ( void );\r
+void MCAN0_Handler ( void );\r
+void MCAN1_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM0_Handler ( void );\r
+void PWM1_Handler ( void );\r
+void QSPI_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RSWDT_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TC9_Handler ( void );\r
+void TC10_Handler ( void );\r
+void TC11_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWIHS0_Handler ( void );\r
+void TWIHS1_Handler ( void );\r
+void TWIHS2_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UART2_Handler ( void );\r
+void UART3_Handler ( void );\r
+void UART4_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USBHS_Handler ( void );\r
+void WDT_Handler ( void );\r
+void XDMAC_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M7 Processor and Core Peripherals \r
+ */\r
+\r
+#define __CM7_REV 0x0000 /**< SAME70Q21 core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAME70Q21 does provide a MPU */\r
+#define __NVIC_PRIO_BITS 3 /**< SAME70Q21 uses 3 Bits for the Priority Levels */\r
+#define __FPU_PRESENT 1 /**< SAME70Q21 does provide a FPU */\r
+#define __FPU_DP 1 /**< SAME70Q21 Double precision FPU */\r
+#define __ICACHE_PRESENT 1 /**< SAME70Q21 does provide an Instruction Cache */\r
+#define __DCACHE_PRESENT 1 /**< SAME70Q21 does provide a Data Cache */\r
+#define __DTCM_PRESENT 1 /**< SAME70Q21 does provide a Data TCM */\r
+#define __ITCM_PRESENT 1 /**< SAME70Q21 does provide an Instruction TCM */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm7.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_same70.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/acc.h"\r
+#include "component/aes.h"\r
+#include "component/afec.h"\r
+#include "component/chipid.h"\r
+#include "component/dacc.h"\r
+#include "component/efc.h"\r
+#include "component/gmac.h"\r
+#include "component/gpbr.h"\r
+#include "component/hsmci.h"\r
+#include "component/icm.h"\r
+#include "component/isi.h"\r
+#include "component/matrix.h"\r
+#include "component/mcan.h"\r
+#include "component/pio.h"\r
+#include "component/pmc.h"\r
+#include "component/pwm.h"\r
+#include "component/qspi.h"\r
+#include "component/rstc.h"\r
+#include "component/rswdt.h"\r
+#include "component/rtc.h"\r
+#include "component/rtt.h"\r
+#include "component/sdramc.h"\r
+#include "component/smc.h"\r
+#include "component/spi.h"\r
+#include "component/ssc.h"\r
+#include "component/supc.h"\r
+#include "component/tc.h"\r
+#include "component/trng.h"\r
+#include "component/twihs.h"\r
+#include "component/uart.h"\r
+#include "component/usart.h"\r
+#include "component/usbhs.h"\r
+#include "component/utmi.h"\r
+#include "component/wdt.h"\r
+#include "component/xdmac.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/hsmci.h"\r
+#include "instance/ssc.h"\r
+#include "instance/spi0.h"\r
+#include "instance/tc0.h"\r
+#include "instance/tc1.h"\r
+#include "instance/tc2.h"\r
+#include "instance/twihs0.h"\r
+#include "instance/twihs1.h"\r
+#include "instance/pwm0.h"\r
+#include "instance/usart0.h"\r
+#include "instance/usart1.h"\r
+#include "instance/usart2.h"\r
+#include "instance/mcan0.h"\r
+#include "instance/mcan1.h"\r
+#include "instance/usbhs.h"\r
+#include "instance/afec0.h"\r
+#include "instance/dacc.h"\r
+#include "instance/acc.h"\r
+#include "instance/icm.h"\r
+#include "instance/isi.h"\r
+#include "instance/gmac.h"\r
+#include "instance/tc3.h"\r
+#include "instance/spi1.h"\r
+#include "instance/pwm1.h"\r
+#include "instance/twihs2.h"\r
+#include "instance/afec1.h"\r
+#include "instance/aes.h"\r
+#include "instance/trng.h"\r
+#include "instance/xdmac.h"\r
+#include "instance/qspi.h"\r
+#include "instance/smc.h"\r
+#include "instance/sdramc.h"\r
+#include "instance/matrix.h"\r
+#include "instance/utmi.h"\r
+#include "instance/pmc.h"\r
+#include "instance/uart0.h"\r
+#include "instance/chipid.h"\r
+#include "instance/uart1.h"\r
+#include "instance/efc.h"\r
+#include "instance/pioa.h"\r
+#include "instance/piob.h"\r
+#include "instance/pioc.h"\r
+#include "instance/piod.h"\r
+#include "instance/pioe.h"\r
+#include "instance/rstc.h"\r
+#include "instance/supc.h"\r
+#include "instance/rtt.h"\r
+#include "instance/wdt.h"\r
+#include "instance/rtc.h"\r
+#include "instance/gpbr.h"\r
+#include "instance/rswdt.h"\r
+#include "instance/uart2.h"\r
+#include "instance/uart3.h"\r
+#include "instance/uart4.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */\r
+#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */\r
+#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */\r
+#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */\r
+#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */\r
+#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */\r
+#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */\r
+#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */\r
+#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */\r
+#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */\r
+#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */\r
+#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */\r
+#define ID_UART2 (44) /**< \brief UART 2 (UART2) */\r
+#define ID_UART3 (45) /**< \brief UART 3 (UART3) */\r
+#define ID_UART4 (46) /**< \brief UART 4 (UART4) */\r
+#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */\r
+#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */\r
+#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */\r
+#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */\r
+#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */\r
+#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */\r
+#define ID_AES (56) /**< \brief AES (AES) */\r
+#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */\r
+#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */\r
+#define ID_ISI (59) /**< \brief Camera Interface (ISI) */\r
+#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */\r
+#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */\r
+#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */\r
+\r
+#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */\r
+#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */\r
+#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */\r
+#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */\r
+#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */\r
+#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES (0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */\r
+#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */\r
+#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */\r
+#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */\r
+#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */\r
+#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */\r
+#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */\r
+#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */\r
+#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */\r
+#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */\r
+#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */\r
+#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */\r
+#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */\r
+#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */\r
+#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */\r
+#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */\r
+#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */\r
+#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */\r
+#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */\r
+#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */\r
+#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */\r
+#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */\r
+#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */\r
+#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */\r
+#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */\r
+#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */\r
+#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */\r
+#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */\r
+#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */\r
+#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */\r
+#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/same70q21.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x200000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (4096u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x60000u)\r
+\r
+#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */\r
+#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */\r
+#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */\r
+#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */\r
+\r
+/* ************************************************************************** */\r
+/* MISCELLANEOUS DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+\r
+#define CHIP_JTAGID (0x05B3D03FUL)\r
+#define CHIP_CIDR (0xA1020E00UL)\r
+#define CHIP_EXID (0x00000002UL)\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAME70Q21 */\r
+/* ************************************************************************** */\r
+\r
+/* %ATMEL_ELECTRICAL% */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (300000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+#define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAME70Q21_ */\r
projects / freertos / blobdiff