Rename DummyTCB_t to StaticTCB_t.

[freertos] / FreeRTOS / Demo / CORTEX_M7_SAME70_Xplained_AtmelStudio / src / config / conf_clock.h

diff --git a/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/config/conf_clock.h b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/config/conf_clock.h
new file mode 100644 (file)
index 0000000..a92ca27
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/config/conf_clock.h
@@ -0,0 +1,104 @@
+/**\r
+ * \file\r
+ *\r
+ * \brief SAME70 clock configuration.\r
+ *\r
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ *    this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ *    this list of conditions and the following disclaimer in the documentation\r
+ *    and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ *    Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef CONF_CLOCK_H_INCLUDED\r
+#define CONF_CLOCK_H_INCLUDED\r
+\r
+// ===== System Clock (MCK) Source Options\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_RC\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_BYPASS\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_4M_RC\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_8M_RC\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_12M_RC\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_BYPASS\r
+#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK\r
+//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_UPLLCK\r
+\r
+// ===== Processor Clock (HCLK) Prescaler Options   (Fhclk = Fsys / (SYSCLK_PRES))\r
+#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_2\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_4\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_8\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_16\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_32\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_64\r
+//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_3\r
+\r
+// ===== System Clock (MCK) Division Options     (Fmck = Fhclk / (SYSCLK_DIV))\r
+#define CONFIG_SYSCLK_DIV            2\r
+\r
+// ===== PLL0 (A) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL0_SOURCE          PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL0_MUL             25\r
+#define CONFIG_PLL0_DIV             1\r
+\r
+// ===== UPLL (UTMI) Hardware fixed at 480 MHz.\r
+\r
+// ===== USB Clock Source Options   (Fusb = FpllX / USB_div)\r
+// Use div effective value here.\r
+//#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL0\r
+#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_UPLL\r
+#define CONFIG_USBCLK_DIV           1\r
+\r
+// ===== Target frequency (Processor clock)\r
+// - XTAL frequency: 12MHz\r
+// - System clock source: PLLA\r
+// - System clock prescaler: 1 (divided by 1)\r
+// - System clock divider: 2 (divided by 2)\r
+// - PLLA source: XTAL\r
+// - PLLA output: XTAL * 25 / 1\r
+// - Processor clock: 12 * 25 / 1 / 1 = 300MHz\r
+// - System clock: 300 / 2 = 150MHz\r
+// ===== Target frequency (USB Clock)\r
+// - USB clock source: UPLL\r
+// - USB clock divider: 1 (not divided)\r
+// - UPLL frequency: 480MHz\r
+// - USB clock: 480 / 1 = 480MHz\r
+\r
+#endif /* CONF_CLOCK_H_INCLUDED */\r