--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ\r
+ * standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. As the interrupt is shared the nesting achieved is not as deep\r
+ * as normal when this test is executed, but still worth while.\r
+ *\r
+ * TC2 channel 0 provides a much higher frequency timer that tests the nesting\r
+ * of interrupts that don't use the FreeRTOS API. For convenience, the high\r
+ * frequency timer also keeps a count of the number of time it executes, and the\r
+ * count is used as the time base for the run time stats (which can be viewed\r
+ * through the CLI).\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 3 (normally 4, if the first two timers used\r
+ * separate interrupts).\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Library includes. */\r
+#include "board.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
+#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
+\r
+/* The channels used in TC0 for generating the three interrupts. */\r
+#define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */\r
+\r
+/* The bit within the RC_SR register that indicates an RC compare. */\r
+#define tmrRC_COMPARE ( 1UL << 4UL )\r
+\r
+/* The high frequency interrupt given a priority above the maximum at which\r
+interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
+timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY\r
+#define tmrHIGHER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/* For convenience the high frequency timer increments a variable that is then\r
+used as the time base for the run time stats. */\r
+volatile uint32_t ulHighFrequencyTimerCounts = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL;\r
+\r
+ /* Enable the TC clocks. */\r
+ PMC_EnablePeripheral( ID_TC0 );\r
+ PMC_EnablePeripheral( ID_TC1 );\r
+\r
+ /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger\r
+ on RC compare. This is part of the IntQTimer test. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger\r
+ on RC compare. This is part of the IntQTimer test. */\r
+ TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider );\r
+ TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure and enable TC0 interrupt on RC compare. */ \r
+ NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TC0_IRQn );\r
+ NVIC_EnableIRQ( TC0_IRQn );\r
+ \r
+ /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on\r
+ RC compare. This is the very high frequency timer. */\r
+ TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_2_FREQUENCY * ulDivider );\r
+ TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS;\r
+\r
+ /* Configure and enable TC1 interrupt on RC compare */ \r
+// NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );\r
+// NVIC_ClearPendingIRQ( TC1_IRQn );\r
+// NVIC_EnableIRQ( TC1_IRQn );\r
+\r
+ TC_Start( TC0, tmrTC0_CHANNEL_0 );\r
+ TC_Start( TC0, tmrTC0_CHANNEL_1 );\r
+// TC_Start( TC1, tmrTC1_CHANNEL_0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TC0_Handler( void )\r
+{\r
+ /* Read will clear the status bit. */\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+\r
+ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 )\r
+ {\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TC1_Handler( void )\r
+{\r
+volatile uint32_t ulDummy;\r
+\r
+ /* Dummy read to clear status bit. */\r
+ ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR;\r
+ NVIC_ClearPendingIRQ( TC1_IRQn );\r
+\r
+ /* Keep a count of the number of interrupts to use as a time base for the\r
+ run-time stats. */\r
+ ulHighFrequencyTimerCounts++;\r
+ \r
+ /* Prevent compiler warnings about the variable being set but then \r
+ unused. */\r
+ ( void ) ulDummy;\r
+}\r
+\r
projects / freertos / blobdiff