--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ */\r
+\r
+void vRegTest1Implementation( void ) __attribute__ ((naked));\r
+void vRegTest2Implementation( void ) __attribute__ ((naked));\r
+\r
+void vRegTest1Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest1LoopCounter \n"\r
+ "/* Fill the core registers with known values. */ \n"\r
+ "mov r0, #100 \n"\r
+ "mov r1, #101 \n"\r
+ "mov r2, #102 \n"\r
+ "mov r3, #103 \n"\r
+ "mov r4, #104 \n"\r
+ "mov r5, #105 \n"\r
+ "mov r6, #106 \n"\r
+ "mov r7, #107 \n"\r
+ "mov r8, #108 \n"\r
+ "mov r9, #109 \n"\r
+ "mov r10, #110 \n"\r
+ "mov r11, #111 \n"\r
+ "mov r12, #112 \n"\r
+\r
+ "/* Fill the VFP registers with known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg1_loop: \n"\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg1_loopf_pass \n"\r
+\r
+ "reg1_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be incorrect. */ \n"\r
+ "b reg1_error_loopf \n"\r
+\r
+ "reg1_loopf_pass: \n"\r
+\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r2, #102 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r3, #103 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r4, #104 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r5, #105 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r6, #106 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r7, #107 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r8, #108 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r9, #109 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r10, #110 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r11, #111 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r12, #112 \n"\r
+ "bne reg1_error_loop \n"\r
+\r
+ "/* Everything passed, increment the loop counter. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =ulRegTest1LoopCounter \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg1_loop \n"\r
+\r
+ "reg1_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "The loop ensures the loop counter stops incrementing. */ \n"\r
+ "b reg1_error_loop \n"\r
+ "nop "\r
+ ); /* __asm volatile. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest2LoopCounter \n"\r
+ "/* Set all the core registers to known values. */ \n"\r
+ "mov r0, #-1 \n"\r
+ "mov r1, #1 \n"\r
+ "mov r2, #2 \n"\r
+ "mov r3, #3 \n"\r
+ "mov r4, #4 \n"\r
+ "mov r5, #5 \n"\r
+ "mov r6, #6 \n"\r
+ "mov r7, #7 \n"\r
+ "mov r8, #8 \n"\r
+ "mov r9, #9 \n"\r
+ "mov r10, #10 \n"\r
+ "mov r11, #11 \n"\r
+ "mov r12, #12 \n"\r
+\r
+ "/* Set all the VFP to known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg2_loop: \n"\r
+\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg2_loopf_pass \n"\r
+\r
+ "reg2_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be \n"\r
+ "incorrect. */ \n"\r
+ "b reg2_error_loopf \n"\r
+\r
+ "reg2_loopf_pass: \n"\r
+\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r2, #2 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r3, #3 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r4, #4 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r5, #5 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r6, #6 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r7, #7 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r8, #8 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r9, #9 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r10, #10 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r11, #11 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r12, #12 \n"\r
+ "bne reg2_error_loop \n"\r
+\r
+ "/* Increment the loop counter to indicate this test is still functioning \n"\r
+ "correctly. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =ulRegTest2LoopCounter \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+\r
+ "/* Yield to increase test coverage. */ \n"\r
+ "movs r0, #0x01 \n"\r
+ "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n"\r
+ "lsl r0, r0, #28 /* Shift to PendSV bit */ \n"\r
+ "str r0, [r1] \n"\r
+ "dsb \n"\r
+\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg2_loop \n"\r
+\r
+ "reg2_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "This loop ensures the loop counter variable stops incrementing. */ \n"\r
+ "b reg2_error_loop \n"\r
+ ); /* __asm volatile */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
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