commit 9f316c246baafa15c542a5aea81a94f26e3d6507

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / CMSIS / cmsis_gcc.h

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
index a99a35927299d4df7422f71004f383c37f4af77e..6ab4511177a3bff60d501595095c1e2c854aef66 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
@@ -1,11 +1,11 @@
 /**************************************************************************//**\r
  * @file     cmsis_gcc.h\r
  * @brief    CMSIS compiler GCC header file\r
- * @version  V5.0.3\r
- * @date     16. January 2018\r
+ * @version  V5.1.0\r
+ * @date     20. December 2018\r
  ******************************************************************************/\r
 /*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
  *\r
  * SPDX-License-Identifier: Apache-2.0\r
  *\r
@@ -246,7 +246,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
  */\r
 __STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
 {\r
-  register uint32_t result;\r
+  uint32_t result;\r
 \r
   __ASM volatile ("MRS %0, psp"  : "=r" (result) );\r
   return(result);\r
@@ -261,7 +261,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
  */\r
 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
 {\r
-  register uint32_t result;\r
+  uint32_t result;\r
 \r
   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );\r
   return(result);\r
@@ -300,7 +300,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
  */\r
 __STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
 {\r
-  register uint32_t result;\r
+  uint32_t result;\r
 \r
   __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
   return(result);\r
@@ -315,7 +315,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
  */\r
 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
 {\r
-  register uint32_t result;\r
+  uint32_t result;\r
 \r
   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
   return(result);\r
@@ -355,7 +355,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
  */\r
 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
 {\r
-  register uint32_t result;\r
+  uint32_t result;\r
 \r
   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
   return(result);\r
@@ -596,7 +596,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
     // without main extensions, the non-secure PSPLIM is RAZ/WI\r
   return 0U;\r
 #else\r
-  register uint32_t result;\r
+  uint32_t result;\r
   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );\r
   return result;\r
 #endif\r
@@ -617,7 +617,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   // without main extensions, the non-secure PSPLIM is RAZ/WI\r
   return 0U;\r
 #else\r
-  register uint32_t result;\r
+  uint32_t result;\r
   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );\r
   return result;\r
 #endif\r
@@ -683,7 +683,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
   // without main extensions, the non-secure MSPLIM is RAZ/WI\r
   return 0U;\r
 #else\r
-  register uint32_t result;\r
+  uint32_t result;\r
   __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
   return result;\r
 #endif\r
@@ -705,7 +705,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
   // without main extensions, the non-secure MSPLIM is RAZ/WI\r
   return 0U;\r
 #else\r
-  register uint32_t result;\r
+  uint32_t result;\r
   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
   return result;\r
 #endif\r
@@ -758,9 +758,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\r
 \r
 \r
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\r
-\r
 /**\r
   \brief   Get FPSCR\r
   \details Returns the current value of the Floating Point Status/Control register.\r
@@ -770,7 +767,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {\r
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
   return __builtin_arm_get_fpscr();\r
 #else\r
@@ -794,7 +793,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 {\r
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\r
-#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
   __builtin_arm_set_fpscr(fpscr);\r
 #else\r
@@ -805,10 +806,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 #endif\r
 }\r
 \r
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\r
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\r
-\r
-\r
 \r
 /*@} end of CMSIS_Core_RegAccFunctions */\r
 \r
@@ -1011,7 +1008,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
   \param [in]  value  Value to count the leading zeros\r
   \return             number of leading zeros in value\r
  */\r
-#define __CLZ             (uint8_t)__builtin_clz\r
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\r
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.\r
+     This guarantees ARM-compatible results if happening to compile on a non-ARM\r
+     target, and ensures the compiler doesn't decide to activate any\r
+     optimisations using the logic "value was passed to __builtin_clz, so it\r
+     is non-zero".\r
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\r
+     single CLZ instruction.\r
+   */\r
+  if (value == 0U)\r
+  {\r
+    return 32U;\r
+  }\r
+  return __builtin_clz(value);\r
+}\r
 \r
 \r
 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\r