/**************************************************************************//**\r
* @file cmsis_gcc.h\r
* @brief CMSIS compiler GCC header file\r
- * @version V5.0.3\r
- * @date 16. January 2018\r
+ * @version V5.1.0\r
+ * @date 20. December 2018\r
******************************************************************************/\r
/*\r
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
*\r
* SPDX-License-Identifier: Apache-2.0\r
*\r
*/\r
__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
{\r
- register uint32_t result;\r
+ uint32_t result;\r
\r
__ASM volatile ("MRS %0, psp" : "=r" (result) );\r
return(result);\r
*/\r
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
{\r
- register uint32_t result;\r
+ uint32_t result;\r
\r
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
return(result);\r
*/\r
__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
{\r
- register uint32_t result;\r
+ uint32_t result;\r
\r
__ASM volatile ("MRS %0, msp" : "=r" (result) );\r
return(result);\r
*/\r
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
{\r
- register uint32_t result;\r
+ uint32_t result;\r
\r
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
return(result);\r
*/\r
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
{\r
- register uint32_t result;\r
+ uint32_t result;\r
\r
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
return(result);\r
// without main extensions, the non-secure PSPLIM is RAZ/WI\r
return 0U;\r
#else\r
- register uint32_t result;\r
+ uint32_t result;\r
__ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
return result;\r
#endif\r
// without main extensions, the non-secure PSPLIM is RAZ/WI\r
return 0U;\r
#else\r
- register uint32_t result;\r
+ uint32_t result;\r
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
return result;\r
#endif\r
// without main extensions, the non-secure MSPLIM is RAZ/WI\r
return 0U;\r
#else\r
- register uint32_t result;\r
+ uint32_t result;\r
__ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
return result;\r
#endif\r
// without main extensions, the non-secure MSPLIM is RAZ/WI\r
return 0U;\r
#else\r
- register uint32_t result;\r
+ uint32_t result;\r
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
return result;\r
#endif\r
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
\r
\r
-#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
-\r
/**\r
\brief Get FPSCR\r
\details Returns the current value of the Floating Point Status/Control register.\r
{\r
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
-#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
return __builtin_arm_get_fpscr();\r
#else\r
{\r
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
-#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
__builtin_arm_set_fpscr(fpscr);\r
#else\r
#endif\r
}\r
\r
-#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
-\r
-\r
\r
/*@} end of CMSIS_Core_RegAccFunctions */\r
\r
\param [in] value Value to count the leading zeros\r
\return number of leading zeros in value\r
*/\r
-#define __CLZ (uint8_t)__builtin_clz\r
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\r
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.\r
+ This guarantees ARM-compatible results if happening to compile on a non-ARM\r
+ target, and ensures the compiler doesn't decide to activate any\r
+ optimisations using the logic "value was passed to __builtin_clz, so it\r
+ is non-zero".\r
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\r
+ single CLZ instruction.\r
+ */\r
+ if (value == 0U)\r
+ {\r
+ return 32U;\r
+ }\r
+ return __builtin_clz(value);\r
+}\r
\r
\r
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r