commit 9f316c246baafa15c542a5aea81a94f26e3d6507

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / CMSIS / cmsis_iccarm.h

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
index 7b3f7f7681c4de9a7f4a044b27ad669cb957e0b7..682849e61032ee6721860f0d4257bc99478318f3 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
@@ -1,8 +1,8 @@
 /**************************************************************************//**\r
  * @file     cmsis_iccarm.h\r
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
- * @version  V5.0.5\r
- * @date     10. January 2018\r
+ * @version  V5.0.8\r
+ * @date     04. September 2018\r
  ******************************************************************************/\r
 \r
 //------------------------------------------------------------------------------\r
@@ -150,7 +150,12 @@
 #endif\r
 \r
 #ifndef   __RESTRICT\r
-  #define __RESTRICT            restrict\r
+  #if __ICCARM_V8\r
+    #define __RESTRICT            __restrict\r
+  #else\r
+    /* Needs IAR language extensions */\r
+    #define __RESTRICT            restrict\r
+  #endif\r
 #endif\r
 \r
 #ifndef   __STATIC_INLINE\r
@@ -340,8 +345,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))\r
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))\r
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))\r
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+\r
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+    // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+    #define __TZ_get_PSPLIM_NS()      (0U)\r
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+  #else\r
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))\r
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+  #endif\r
+\r
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))\r
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))\r
 \r
@@ -716,12 +730,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\r
     {\r
       uint32_t res;\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      res = 0U;\r
+    #else\r
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));\r
+    #endif\r
       return res;\r
     }\r
+\r
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\r
     {\r
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\r
+      // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+      (void)value;\r
+    #else\r
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));\r
+    #endif\r
     }\r
 \r
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\r
@@ -826,78 +853,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return ((uint8_t)res);\r
   }\r
 \r
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return ((uint16_t)res);\r
   }\r
 \r
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return res;\r
   }\r
 \r
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
   {\r
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
   }\r
 \r
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
   {\r
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
   }\r
 \r
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
   {\r
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
   }\r
 \r
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return ((uint8_t)res);\r
   }\r
 \r
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return ((uint16_t)res);\r
   }\r
 \r
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
     return res;\r
   }\r
 \r
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
     return res;\r
   }\r
 \r
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
     return res;\r
   }\r
 \r
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
   {\r
     uint32_t res;\r
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
     return res;\r
   }\r
 \r