commit 9f316c246baafa15c542a5aea81a94f26e3d6507

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / CMSIS / mpu_armv8.h

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
index 656ca6b551f793978b7bb80c8aed4509cca03dab..2fe28b687f2276ba20ef9598d73a7d41f396b350 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h
@@ -1,11 +1,11 @@
 /******************************************************************************\r
  * @file     mpu_armv8.h\r
- * @brief    CMSIS MPU API for Armv8-M MPU\r
- * @version  V5.0.4\r
- * @date     10. January 2018\r
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU\r
+ * @version  V5.1.0\r
+ * @date     08. March 2019\r
  ******************************************************************************/\r
 /*\r
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.\r
  *\r
  * SPDX-License-Identifier: Apache-2.0\r
  *\r
@@ -87,7 +87,7 @@
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
 */\r
 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
-  ((BASE & MPU_RBAR_BASE_Pos) | \\r
+  ((BASE & MPU_RBAR_BASE_Msk) | \\r
   ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
   ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
   ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
@@ -101,6 +101,21 @@
   ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
   (MPU_RLAR_EN_Msk))\r
 \r
+#if defined(MPU_RLAR_PXN_Pos)\r
+  \r
+/** \brief Region Limit Address Register with PXN value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \\r
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \\r
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+  (MPU_RLAR_EN_Msk))\r
+  \r
+#endif\r
+\r
 /**\r
 * Struct for a single MPU Region\r
 */\r
@@ -114,20 +129,19 @@ typedef struct {
 */\r
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
 {\r
-  __DSB();\r
-  __ISB();\r
   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
 #endif\r
+  __DSB();\r
+  __ISB();\r
 }\r
 \r
 /** Disable the MPU.\r
 */\r
 __STATIC_INLINE void ARM_MPU_Disable(void)\r
 {\r
-  __DSB();\r
-  __ISB();\r
+  __DMB();\r
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
 #endif\r
@@ -140,20 +154,19 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
 */\r
 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
 {\r
-  __DSB();\r
-  __ISB();\r
   MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
 #endif\r
+  __DSB();\r
+  __ISB();\r
 }\r
 \r
 /** Disable the Non-secure MPU.\r
 */\r
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
 {\r
-  __DSB();\r
-  __ISB();\r
+  __DMB();\r
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
 #endif\r
@@ -267,7 +280,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 * \param src Source data is copied from.\r
 * \param len Amount of data words to be copied.\r
 */\r
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
 {\r
   uint32_t i;\r
   for (i = 0U; i < len; ++i) \r
@@ -287,7 +300,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
   if (cnt == 1U) {\r
     mpu->RNR = rnr;\r
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
   } else {\r
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\r
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
@@ -295,7 +308,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
     mpu->RNR = rnrBase;\r
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
       table += c;\r
       cnt -= c;\r
       rnrOffset = 0U;\r
@@ -303,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       mpu->RNR = rnrBase;\r
     }\r
     \r
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
   }\r
 }\r
 \r