Add ARMv8M demo project for NXP LPC55S69.

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / board / pin_mux.c

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/pin_mux.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/pin_mux.c
new file mode 100644 (file)
index 0000000..62fd16e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/board/pin_mux.c
@@ -0,0 +1,99 @@
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+\r
+/* clang-format off */\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Pins v5.0\r
+processor: LPC55S69\r
+package_id: LPC55S69JBD100\r
+mcu_data: ksdk2_0\r
+processor_version: 0.0.6\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+/* clang-format on */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_iocon.h"\r
+#include "pin_mux.h"\r
+\r
+/* FUNCTION ************************************************************************************************************\r
+ *\r
+ * Function Name : BOARD_InitBootPins\r
+ * Description   : Calls initialization functions.\r
+ *\r
+ * END ****************************************************************************************************************/\r
+void BOARD_InitBootPins(void)\r
+{\r
+    BOARD_InitPins();\r
+}\r
+\r
+/* clang-format off */\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+BOARD_InitPins:\r
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}\r
+- pin_list:\r
+  - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,\r
+    mode: inactive, slew_rate: standard, invert: disabled, digi_mode: digital, open_drain: disabled}\r
+  - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,\r
+    slew_rate: standard, invert: disabled, digi_mode: digital, open_drain: disabled}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+/* clang-format on */\r
+\r
+/* FUNCTION ************************************************************************************************************\r
+ *\r
+ * Function Name : BOARD_InitPins\r
+ * Description   : Configures pin routing and optionally pin electrical features.\r
+ *\r
+ * END ****************************************************************************************************************/\r
+/* Function assigned for the Cortex-M33 (Core #0) */\r
+void BOARD_InitPins(void)\r
+{\r
+    /* Enables the clock for the I/O controller.: Enable Clock. */\r
+    CLOCK_EnableClock(kCLOCK_Iocon);\r
+\r
+    const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */\r
+                                         IOCON_PIO_FUNC1 |\r
+                                         /* No addition pin function */\r
+                                         IOCON_PIO_MODE_INACT |\r
+                                         /* Standard mode, output slew rate control is enabled */\r
+                                         IOCON_PIO_SLEW_STANDARD |\r
+                                         /* Input function is not inverted */\r
+                                         IOCON_PIO_INV_DI |\r
+                                         /* Enables digital function */\r
+                                         IOCON_PIO_DIGITAL_EN |\r
+                                         /* Open drain is disabled */\r
+                                         IOCON_PIO_OPENDRAIN_DI);\r
+    /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */\r
+    IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);\r
+\r
+    const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */\r
+                                         IOCON_PIO_FUNC1 |\r
+                                         /* No addition pin function */\r
+                                         IOCON_PIO_MODE_INACT |\r
+                                         /* Standard mode, output slew rate control is enabled */\r
+                                         IOCON_PIO_SLEW_STANDARD |\r
+                                         /* Input function is not inverted */\r
+                                         IOCON_PIO_INV_DI |\r
+                                         /* Enables digital function */\r
+                                         IOCON_PIO_DIGITAL_EN |\r
+                                         /* Open drain is disabled */\r
+                                         IOCON_PIO_OPENDRAIN_DI);\r
+    /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */\r
+    IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);\r
+}\r
+/***********************************************************************************************************************\r
+ * EOF\r
+ **********************************************************************************************************************/\r