-#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U)\r
-#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U)\r
-#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)\r
-#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U)\r
-#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U)\r
-#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)\r
-#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU)\r
-#define SYSCON_PLL0SSCG1_MF_SHIFT (2U)\r
-#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)\r
-#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U)\r
-#define SYSCON_PLL0SSCG1_MR_SHIFT (5U)\r
-#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)\r
-#define SYSCON_PLL0SSCG1_MC_MASK (0x300U)\r
-#define SYSCON_PLL0SSCG1_MC_SHIFT (8U)\r
-#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)\r
-#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U)\r
-#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U)\r
-#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)\r
-#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U)\r
-#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U)\r
-#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)\r
-#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U)\r
-#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U)\r
-#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)\r
-#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U)\r
-#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U)\r
-#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)\r
-/*! @} */\r
-\r
-/*! @name EFUSECLKCTRL - eFUSE controller clock enable */\r
-/*! @{ */\r
-#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U)\r
-#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U)\r
-#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK)\r
-/*! @} */\r
-\r
-/*! @name STARTER - Start logic wake-up enable register */\r
-/*! @{ */\r
-#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U)\r
-#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U)\r
-/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK)\r
-#define SYSCON_STARTER_SYS_MASK (0x1U)\r
-#define SYSCON_STARTER_SYS_SHIFT (0U)\r
-/*! SYS - SYS interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK)\r
-#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U)\r
-#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U)\r
-/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK)\r
-#define SYSCON_STARTER_SDMA0_MASK (0x2U)\r
-#define SYSCON_STARTER_SDMA0_SHIFT (1U)\r
-/*! SDMA0 - SDMA0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK)\r
-#define SYSCON_STARTER_GINT0_MASK (0x4U)\r
-#define SYSCON_STARTER_GINT0_SHIFT (2U)\r
-/*! GINT0 - GINT0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)\r
-#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U)\r
-#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U)\r
-/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK)\r
-#define SYSCON_STARTER_GINT1_MASK (0x8U)\r
-#define SYSCON_STARTER_GINT1_SHIFT (3U)\r
-/*! GINT1 - GINT1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)\r
-#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U)\r
-#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U)\r
-/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK)\r
-#define SYSCON_STARTER_CTIMER2_MASK (0x10U)\r
-#define SYSCON_STARTER_CTIMER2_SHIFT (4U)\r
-/*! CTIMER2 - CTIMER2 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)\r
-#define SYSCON_STARTER_PIO_INT0_MASK (0x10U)\r
-#define SYSCON_STARTER_PIO_INT0_SHIFT (4U)\r
-/*! PIO_INT0 - PIO_INT0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK)\r
-#define SYSCON_STARTER_CTIMER4_MASK (0x20U)\r
-#define SYSCON_STARTER_CTIMER4_SHIFT (5U)\r
-/*! CTIMER4 - CTIMER4 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)\r
-#define SYSCON_STARTER_PIO_INT1_MASK (0x20U)\r
-#define SYSCON_STARTER_PIO_INT1_SHIFT (5U)\r
-/*! PIO_INT1 - PIO_INT1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK)\r
-#define SYSCON_STARTER_OS_EVENT_MASK (0x40U)\r
-#define SYSCON_STARTER_OS_EVENT_SHIFT (6U)\r
-/*! OS_EVENT - OS_EVENT interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK)\r
-#define SYSCON_STARTER_PIO_INT2_MASK (0x40U)\r
-#define SYSCON_STARTER_PIO_INT2_SHIFT (6U)\r
-/*! PIO_INT2 - PIO_INT2 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK)\r
-#define SYSCON_STARTER_PIO_INT3_MASK (0x80U)\r
-#define SYSCON_STARTER_PIO_INT3_SHIFT (7U)\r
-/*! PIO_INT3 - PIO_INT3 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK)\r
-#define SYSCON_STARTER_UTICK0_MASK (0x100U)\r
-#define SYSCON_STARTER_UTICK0_SHIFT (8U)\r
-/*! UTICK0 - UTICK0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK)\r
-#define SYSCON_STARTER_MRT0_MASK (0x200U)\r
-#define SYSCON_STARTER_MRT0_SHIFT (9U)\r
-/*! MRT0 - MRT0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK)\r
-#define SYSCON_STARTER_CTIMER0_MASK (0x400U)\r
-#define SYSCON_STARTER_CTIMER0_SHIFT (10U)\r
-/*! CTIMER0 - CTIMER0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)\r
-#define SYSCON_STARTER_SDIO_MASK (0x400U)\r
-#define SYSCON_STARTER_SDIO_SHIFT (10U)\r
-/*! SDIO - SDIO interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK)\r
-#define SYSCON_STARTER_CTIMER1_MASK (0x800U)\r
-#define SYSCON_STARTER_CTIMER1_SHIFT (11U)\r
-/*! CTIMER1 - CTIMER1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)\r
-#define SYSCON_STARTER_SCT0_MASK (0x1000U)\r
-#define SYSCON_STARTER_SCT0_SHIFT (12U)\r
-/*! SCT0 - SCT0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)\r
-#define SYSCON_STARTER_CTIMER3_MASK (0x2000U)\r
-#define SYSCON_STARTER_CTIMER3_SHIFT (13U)\r
-/*! CTIMER3 - CTIMER3 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)\r
-#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U)\r
-#define SYSCON_STARTER_FLEXINT0_SHIFT (14U)\r
-/*! FLEXINT0 - FLEXINT0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK)\r
-#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U)\r
-#define SYSCON_STARTER_FLEXINT1_SHIFT (15U)\r
-/*! FLEXINT1 - FLEXINT1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK)\r
-#define SYSCON_STARTER_USB1_MASK (0x8000U)\r
-#define SYSCON_STARTER_USB1_SHIFT (15U)\r
-/*! USB1 - USB1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)\r
-#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U)\r
-#define SYSCON_STARTER_FLEXINT2_SHIFT (16U)\r
-/*! FLEXINT2 - FLEXINT2 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK)\r
-#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U)\r
-#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U)\r
-/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK)\r
-#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U)\r
-#define SYSCON_STARTER_FLEXINT3_SHIFT (17U)\r
-/*! FLEXINT3 - FLEXINT3 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK)\r
-#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U)\r
-#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U)\r
-/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK)\r
-#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U)\r
-#define SYSCON_STARTER_FLEXINT4_SHIFT (18U)\r
-/*! FLEXINT4 - FLEXINT4 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK)\r
-#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U)\r
-#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U)\r
-/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK)\r
-#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U)\r
-#define SYSCON_STARTER_FLEXINT5_SHIFT (19U)\r
-/*! FLEXINT5 - FLEXINT5 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK)\r
-#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U)\r
-#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U)\r
-/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK)\r
-#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U)\r
-#define SYSCON_STARTER_FLEXINT6_SHIFT (20U)\r
-/*! FLEXINT6 - FLEXINT6 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK)\r
-#define SYSCON_STARTER_PLU_MASK (0x100000U)\r
-#define SYSCON_STARTER_PLU_SHIFT (20U)\r
-/*! PLU - PLU interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK)\r
-#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U)\r
-#define SYSCON_STARTER_FLEXINT7_SHIFT (21U)\r
-/*! FLEXINT7 - FLEXINT7 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK)\r
-#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U)\r
-#define SYSCON_STARTER_SEC_VIO_SHIFT (21U)\r
-/*! SEC_VIO - SEC_VIO interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK)\r
-#define SYSCON_STARTER_ADC0_MASK (0x400000U)\r
-#define SYSCON_STARTER_ADC0_SHIFT (22U)\r
-/*! ADC0 - ADC0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK)\r
-#define SYSCON_STARTER_SHA_MASK (0x400000U)\r
-#define SYSCON_STARTER_SHA_SHIFT (22U)\r
-/*! SHA - SHA interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK)\r
-#define SYSCON_STARTER_CASER_MASK (0x800000U)\r
-#define SYSCON_STARTER_CASER_SHIFT (23U)\r
-/*! CASER - CASER interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK)\r
-#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U)\r
-#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U)\r
-/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK)\r
-#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U)\r
-#define SYSCON_STARTER_QDDKEY_SHIFT (24U)\r
-/*! QDDKEY - QDDKEY interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK)\r
-#define SYSCON_STARTER_PQ_MASK (0x2000000U)\r
-#define SYSCON_STARTER_PQ_SHIFT (25U)\r
-/*! PQ - PQ interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK)\r
-#define SYSCON_STARTER_SDMA1_MASK (0x4000000U)\r
-#define SYSCON_STARTER_SDMA1_SHIFT (26U)\r
-/*! SDMA1 - SDMA1 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK)\r
-#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U)\r
-#define SYSCON_STARTER_LSPI_HS_SHIFT (27U)\r
-/*! LSPI_HS - LSPI_HS interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK)\r
-#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)\r
-#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)\r
-/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)\r
-#define SYSCON_STARTER_USB0_MASK (0x10000000U)\r
-#define SYSCON_STARTER_USB0_SHIFT (28U)\r
-/*! USB0 - USB0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)\r
-#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U)\r
-#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U)\r
-/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK)\r
-#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U)\r
-#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U)\r
-/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK)\r
-#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U)\r
-#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U)\r
-#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK)\r
-#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U)\r
-#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U)\r
-/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up.\r
- * 0b0..Wake-up disabled.\r
- * 0b1..Wake-up enabled.\r
- */\r
-#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK)\r
-/*! @} */\r
-\r
-/* The count of SYSCON_STARTER */\r
-#define SYSCON_STARTER_COUNT (2U)\r
-\r
-/*! @name STARTERSET - Set bits in STARTER */\r
-/*! @{ */\r
-#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U)\r
-#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U)\r
-#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK)\r
-#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U)\r
-#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U)\r
-#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U)\r
-#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U)\r
-#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK)\r
-#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U)\r
-#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U)\r
-#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U)\r
-#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U)\r
-#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U)\r
-#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U)\r
-#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U)\r
-#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK)\r
-#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U)\r
-#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U)\r
-#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U)\r
-#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U)\r
-#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK)\r
-#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U)\r
-#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U)\r
-#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U)\r
-#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U)\r
-#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U)\r
-#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U)\r
-#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK)\r
-#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U)\r
-#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U)\r
-#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK)\r
-#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U)\r
-#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U)\r
-#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK)\r
-#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U)\r
-#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U)\r
-#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK)\r
-#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U)\r
-#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U)\r
-#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK)\r
-#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U)\r
-#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U)\r
-#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK)\r
-#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U)\r
-#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U)\r
-#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK)\r
-#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U)\r
-#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U)\r
-#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK)\r
-#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U)\r
-#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U)\r
-#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK)\r
-#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U)\r
-#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U)\r
-#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U)\r
-#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U)\r
-#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U)\r
-#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U)\r
-#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK)\r
-#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U)\r
-#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U)\r
-#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U)\r
-#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U)\r
-#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK)\r
-#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U)\r
-#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U)\r
-#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U)\r
-#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U)\r
-#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK)\r
-#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U)\r
-#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U)\r
-#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U)\r
-#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U)\r
-#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U)\r
-#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U)\r
-#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U)\r
-#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U)\r
-#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U)\r
-#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK)\r
-#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U)\r
-#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U)\r
-#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK)\r
-#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U)\r
-#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U)\r
-#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK)\r
-#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U)\r
-#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U)\r
-#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK)\r
-#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U)\r
-#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U)\r
-#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK)\r
-#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U)\r
-#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U)\r
-#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK)\r
-#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U)\r
-#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U)\r
-#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK)\r
-#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U)\r
-#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U)\r
-#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK)\r
-#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U)\r
-#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U)\r
-#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK)\r
-#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U)\r
-#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U)\r
-#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK)\r
-#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U)\r
-#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U)\r
-#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK)\r
-#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U)\r
-#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U)\r
-#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK)\r
-#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U)\r
-#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U)\r
-#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK)\r
-#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U)\r
-#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U)\r
-#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK)\r
-#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U)\r
-#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U)\r
-#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK)\r
-#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U)\r
-#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U)\r
-#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK)\r
-#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U)\r
-#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U)\r
-#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK)\r
-#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U)\r
-#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U)\r
-#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK)\r
-/*! @} */\r
-\r
-/* The count of SYSCON_STARTERSET */\r
-#define SYSCON_STARTERSET_COUNT (2U)\r
-\r
-/*! @name STARTERCLR - Clear bits in STARTER */\r
-/*! @{ */\r
-#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U)\r
-#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U)\r
-#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U)\r
-#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U)\r
-#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U)\r
-#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U)\r
-#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U)\r
-#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U)\r
-#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U)\r
-#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U)\r
-#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U)\r
-#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U)\r
-#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U)\r
-#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U)\r
-#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U)\r
-#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U)\r
-#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U)\r
-#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U)\r
-#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U)\r
-#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U)\r
-#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U)\r
-#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U)\r
-#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U)\r
-#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK)\r
-#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U)\r
-#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U)\r
-#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK)\r
-#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U)\r
-#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U)\r
-#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK)\r
-#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U)\r
-#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U)\r
-#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U)\r
-#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U)\r
-#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U)\r
-#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U)\r
-#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U)\r
-#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U)\r
-#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U)\r
-#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U)\r
-#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U)\r
-#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U)\r
-#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U)\r
-#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U)\r
-#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U)\r
-#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U)\r
-#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U)\r
-#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U)\r
-#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK)\r
-#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U)\r
-#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U)\r
-#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U)\r
-#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U)\r
-#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK)\r
-#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U)\r
-#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U)\r
-#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U)\r
-#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U)\r
-#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U)\r
-#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U)\r
-#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U)\r
-#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U)\r
-#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U)\r
-#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U)\r
-#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U)\r
-#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U)\r
-#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U)\r
-#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK)\r
-#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U)\r
-#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U)\r
-#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK)\r
-#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U)\r
-#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U)\r
-#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U)\r
-#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U)\r
-#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK)\r
-#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U)\r
-#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U)\r
-#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U)\r
-#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U)\r
-#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK)\r
-#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U)\r
-#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U)\r
-#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK)\r
-#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U)\r
-#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U)\r
-#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK)\r
-#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U)\r
-#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U)\r
-#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK)\r
-#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U)\r
-#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U)\r
-#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK)\r
-#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U)\r
-#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U)\r
-#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK)\r
-#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U)\r
-#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U)\r
-#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK)\r
-#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U)\r
-#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U)\r
-#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK)\r
-#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U)\r
-#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U)\r
-#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U)\r
-#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U)\r
-#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U)\r
-#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U)\r
-#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK)\r
-#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U)\r
-#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U)\r
-#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK)\r
-#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U)\r
-#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U)\r
-#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK)\r
-/*! @} */\r
-\r
-/* The count of SYSCON_STARTERCLR */\r
-#define SYSCON_STARTERCLR_COUNT (2U)\r
-\r
-/*! @name HARDWARESLEEP - Hardware Sleep control */\r
-/*! @{ */\r
-#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U)\r
-#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U)\r
-#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK)\r
-#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U)\r
-#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U)\r
-#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK)\r
-#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U)\r
-#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U)\r
-#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK)\r
-#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U)\r
-#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U)\r
-#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK)\r