commit 9f316c246baafa15c542a5aea81a94f26e3d6507

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / device / LPC55S69_cm33_core0_features.h

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
index 777e83d99f4368db86a6ea5e261fc3fc5282e561..b8c24e2b5d87ec9a9d34e71241a7aebe2fc6dedc 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
@@ -1,7 +1,7 @@
 /*\r
 ** ###################################################################\r
-**     Version:             rev. 1.0, 2018-08-22\r
-**     Build:               b190122\r
+**     Version:             rev. 1.1, 2019-05-16\r
+**     Build:               b190719\r
 **\r
 **     Abstract:\r
 **         Chip specific module features.\r
@@ -18,6 +18,8 @@
 **     Revisions:\r
 **     - rev. 1.0 (2018-08-22)\r
 **         Initial version based on v0.2UM\r
+**     - rev. 1.1 (2019-05-16)\r
+**         Initial A1 version based on v1.3UM\r
 **\r
 ** ###################################################################\r
 */\r
@@ -108,6 +110,8 @@
 \r
 /* @brief FIFO availability on the SoC. */\r
 #define FSL_FEATURE_LPADC_FIFO_COUNT (2)\r
+/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)\r
 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */\r
 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)\r
 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */\r
@@ -134,6 +138,14 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)\r
 /* @brief Has offset trim (register OFSTRIM). */\r
 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)\r
+/* @brief Has internal temperature sensor. */\r
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)\r
+/* @brief Temperature sensor parameter A (slope). */\r
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)\r
+/* @brief Temperature sensor parameter B (offset). */\r
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)\r
+/* @brief Temperature sensor parameter Alpha. */\r
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)\r
 \r
 /* CASPER module features */\r
 \r
@@ -141,11 +153,88 @@
 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)\r
 /* @brief Interleaving of the CASPER dedicated RAM */\r
 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)\r
+/* @brief CASPER dedicated RAM offset */\r
+#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)\r
 \r
 /* DMA module features */\r
 \r
 /* @brief Number of channels */\r
-#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)\r
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)\r
+/* @brief Align size of DMA descriptor */\r
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)\r
+/* @brief DMA head link descriptor table align size */\r
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)\r
+\r
+/* FLEXCOMM module features */\r
+\r
+/* @brief FLEXCOMM0 USART INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)\r
+/* @brief FLEXCOMM0 SPI INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)\r
+/* @brief FLEXCOMM0 I2C INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)\r
+/* @brief FLEXCOMM0 I2S INDEX 0 */\r
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)\r
+/* @brief FLEXCOMM1 USART INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)\r
+/* @brief FLEXCOMM1 SPI INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)\r
+/* @brief FLEXCOMM1 I2C INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)\r
+/* @brief FLEXCOMM1 I2S INDEX 1 */\r
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)\r
+/* @brief FLEXCOMM2 USART INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)\r
+/* @brief FLEXCOMM2 SPI INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)\r
+/* @brief FLEXCOMM2 I2C INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)\r
+/* @brief FLEXCOMM2 I2S INDEX 2 */\r
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)\r
+/* @brief FLEXCOMM3 USART INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)\r
+/* @brief FLEXCOMM3 SPI INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)\r
+/* @brief FLEXCOMM3 I2C INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)\r
+/* @brief FLEXCOMM3 I2S INDEX 3 */\r
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)\r
+/* @brief FLEXCOMM4 USART INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)\r
+/* @brief FLEXCOMM4 SPI INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)\r
+/* @brief FLEXCOMM4 I2C INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)\r
+/* @brief FLEXCOMM4 I2S INDEX 4 */\r
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)\r
+/* @brief FLEXCOMM5 USART INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)\r
+/* @brief FLEXCOMM5 SPI INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)\r
+/* @brief FLEXCOMM5 I2C INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)\r
+/* @brief FLEXCOMM5 I2S INDEX 5 */\r
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)\r
+/* @brief FLEXCOMM6 USART INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)\r
+/* @brief FLEXCOMM6 SPI INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)\r
+/* @brief FLEXCOMM6 I2C INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)\r
+/* @brief FLEXCOMM6 I2S INDEX 6 */\r
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)\r
+/* @brief FLEXCOMM7 USART INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)\r
+/* @brief FLEXCOMM7 SPI INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)\r
+/* @brief FLEXCOMM7 I2C INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)\r
+/* @brief FLEXCOMM7 I2S INDEX 7 */\r
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)\r
+/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */\r
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)\r
+/* @brief I2S has DMIC interconnection */\r
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)\r
 \r
 /* HASHCRYPT module features */\r
 \r
@@ -155,7 +244,9 @@
 /* I2S module features */\r
 \r
 /* @brief I2S support dual channel transfer. */\r
-#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)\r
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)\r
+/* @brief I2S has DMIC interconnection. */\r
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)\r
 \r
 /* IOCON module features */\r
 \r
@@ -170,22 +261,27 @@
 /* MRT module features */\r
 \r
 /* @brief number of channels. */\r
-#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)\r
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)\r
 \r
 /* PINT module features */\r
 \r
 /* @brief Number of connected outputs */\r
-#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)\r
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)\r
+\r
+/* PLU module features */\r
+\r
+/* @brief Has WAKEINT_CTRL register. */\r
+#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)\r
 \r
 /* POWERLIB module features */\r
 \r
-/* @brief Niobe4's Powerlib API is different with other LPC series devices. */\r
-#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)\r
+/* @brief Powerlib API is different with other LPC series devices. */\r
+#define FSL_FEATURE_POWERLIB_EXTEND (1)\r
 \r
 /* POWERQUAD module features */\r
 \r
 /* @brief Sine and Cossine fix errata */\r
-#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA  (1)\r
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)\r
 \r
 /* PUF module features */\r
 \r
@@ -208,13 +304,13 @@
 /* SDIF module features */\r
 \r
 /* @brief FIFO depth, every location is a WORD */\r
-#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)\r
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)\r
 /* @brief Max DMA buffer size */\r
-#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)\r
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)\r
 /* @brief Max source clock in HZ */\r
-#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)\r
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)\r
 /* @brief support 2 cards */\r
-#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD  (1)\r
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)\r
 \r
 /* SECPINT module features */\r
 \r
@@ -235,6 +331,8 @@
 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)\r
 /* @brief CCM_ANALOG availability on the SoC.  */\r
 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)\r
+/* @brief Starter register discontinuous. */\r
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)\r
 \r
 /* USB module features */\r
 \r
@@ -289,4 +387,3 @@
 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)\r
 \r
 #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */\r
-\r