/*\r
** ###################################################################\r
** Processors: LPC55S69JBD100_cm33_core0\r
-** LPC55S69JET98_cm33_core0\r
+** LPC55S69JBD64_cm33_core0\r
+** LPC55S69JEV98_cm33_core0\r
**\r
** Compilers: GNU C Compiler\r
** IAR ANSI C/C++ Compiler for ARM\r
** Keil ARM C/C++ Compiler\r
** MCUXpresso Compiler\r
**\r
-** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018\r
-** Version: rev. 1.0, 2018-08-22\r
-** Build: b181219\r
+** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019\r
+** Version: rev. 1.1, 2019-05-16\r
+** Build: b190830\r
**\r
** Abstract:\r
** Provides a system configuration function and a global variable that\r
** the oscillator (PLL) that is part of the microcontroller device.\r
**\r
** Copyright 2016 Freescale Semiconductor, Inc.\r
-** Copyright 2016-2018 NXP\r
+** Copyright 2016-2019 NXP\r
** All rights reserved.\r
**\r
** SPDX-License-Identifier: BSD-3-Clause\r
** Revisions:\r
** - rev. 1.0 (2018-08-22)\r
** Initial version based on v0.2UM\r
+** - rev. 1.1 (2019-05-16)\r
+** Initial A1 version based on v1.3UM\r
**\r
** ###################################################################\r
*/\r
\r
/*!\r
* @file LPC55S69_cm33_core0\r
- * @version 1.0\r
- * @date 2018-08-22\r
+ * @version 1.1\r
+ * @date 2019-05-16\r
* @brief Device specific configuration file for LPC55S69_cm33_core0\r
* (implementation file)\r
*\r
}\r
else\r
{\r
- mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);\r
- mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));\r
- mMult = (float)mMult_int + mMult_fract;\r
+ mMult_int =\r
+ ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);\r
+ mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / (1 << PLL_SSCG_MD_INT_P));\r
+ mMult = (float)mMult_int + mMult_fract;\r
}\r
if (mMult == 0)\r
{\r
*/\r
static uint32_t CLOCK_GetFro12MFreq(void)\r
{\r
- return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
- 0 :\r
- (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;\r
+ return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;\r
}\r
\r
/* Get FRO 1M Clk */\r
*/\r
static uint32_t CLOCK_GetFroHfFreq(void)\r
{\r
- return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
- 0 :\r
- (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;\r
+ return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;\r
}\r
\r
/* Get RTC OSC Clk */\r
*/\r
static uint32_t CLOCK_GetOsc32KFreq(void)\r
{\r
- return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?\r
+ return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?\r
CLK_RTC_32K_CLK :\r
- ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?\r
+ ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ?\r
CLK_RTC_32K_CLK :\r
0U;\r
}\r
\r
-\r
-\r
/* ----------------------------------------------------------------------------\r
-- Core clock\r
---------------------------------------------------------------------------- */\r
-- SystemInit()\r
---------------------------------------------------------------------------- */\r
\r
-__attribute__ ((weak)) void SystemInit (void) {\r
+__attribute__((weak)) void SystemInit(void)\r
+{\r
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\r
- SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */\r
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */\r
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */\r
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Normal mode */\r
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */\r
\r
- SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */\r
+ SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */\r
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ SCB_NS->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */\r
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
\r
- SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */\r
+ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */\r
\r
#if defined(__MCUXPRESSO)\r
- extern void(*const g_pfnVectors[]) (void);\r
- SCB->VTOR = (uint32_t) &g_pfnVectors;\r
+ extern void (*const g_pfnVectors[])(void);\r
+ SCB->VTOR = (uint32_t)&g_pfnVectors;\r
#else\r
extern void *__Vectors;\r
- SCB->VTOR = (uint32_t) &__Vectors;\r
+ SCB->VTOR = (uint32_t)&__Vectors;\r
#endif\r
SYSCON->TRACECLKDIV = 0;\r
/* Optionally enable RAM banks that may be off by default at reset */\r
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)\r
- SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK\r
- | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;\r
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK |\r
+ SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;\r
#endif\r
- SystemInitHook();\r
+ SystemInitHook();\r
}\r
\r
/* ----------------------------------------------------------------------------\r
-- SystemCoreClockUpdate()\r
---------------------------------------------------------------------------- */\r
\r
-void SystemCoreClockUpdate (void) {\r
+void SystemCoreClockUpdate(void)\r
+{\r
uint32_t clkRate = 0;\r
uint32_t prediv, postdiv;\r
float workRate;\r
default:\r
break;\r
}\r
- if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))\r
+ if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) &&\r
+ (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) &&\r
+ ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) &&\r
+ ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))\r
{\r
- prediv = findPll0PreDiv();\r
+ prediv = findPll0PreDiv();\r
postdiv = findPll0PostDiv();\r
/* Adjust input clock */\r
clkRate = clkRate / prediv;\r
/* MDEC used for rate */\r
workRate = (float)clkRate * (float)findPll0MMult();\r
- clkRate = (uint32_t)(workRate / ((float)postdiv));\r
+ clkRate = (uint32_t)(workRate / ((float)postdiv));\r
}\r
break;\r
case 0x02: /* PLL1 clock (pll1_clk)*/\r
default:\r
break;\r
}\r
- if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))\r
+ if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) &&\r
+ (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) &&\r
+ ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))\r
{\r
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */\r
- prediv = findPll1PreDiv();\r
+ prediv = findPll1PreDiv();\r
postdiv = findPll1PostDiv();\r
/* Adjust input clock */\r
clkRate = clkRate / prediv;\r
\r
/* MDEC used for rate */\r
workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();\r
- clkRate = workRate1 / ((uint64_t)postdiv);\r
+ clkRate = workRate1 / ((uint64_t)postdiv);\r
}\r
break;\r
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
-- SystemInitHook()\r
---------------------------------------------------------------------------- */\r
\r
-__attribute__ ((weak)) void SystemInitHook (void) {\r
- /* Void implementation of the weak function. */\r
+__attribute__((weak)) void SystemInitHook(void)\r
+{\r
+ /* Void implementation of the weak function. */\r
}\r
projects / freertos / blobdiff