/*\r
- * Copyright (c) 2017 - 2018 , NXP\r
+ * Copyright 2017 - 2019 , NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
*/\r
\r
-#include "fsl_common.h"\r
#include "fsl_clock.h"\r
#include "fsl_power.h"\r
/*******************************************************************************\r
!!! If required these #defines can be moved to chip library file\r
----------------------------------------------------------------------------*/\r
\r
-#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */\r
-#define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */\r
-#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */\r
+#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */\r
+#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P)\r
+#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */\r
#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)\r
#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */\r
#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)\r
\r
#define PLL_MIN_CCO_FREQ_MHZ (275000000U)\r
#define PLL_MAX_CCO_FREQ_MHZ (550000000U)\r
-#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */\r
+#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */\r
#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */\r
#define PLL_MIN_IN_SSMODE (3000000U)\r
-#define PLL_MAX_IN_SSMODE (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */\r
+#define PLL_MAX_IN_SSMODE \\r
+ (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */\r
\r
/* PLL NDEC reg */\r
#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)\r
/* PLL PDEC reg */\r
#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)\r
-/* SSCG control0 */\r
-#define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M)\r
+/* SSCG control1 */\r
+#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M)\r
\r
/* PLL0 SSCG control1 */\r
#define PLL0_SSCG_MD_FRACT_P 0U\r
/** External clock rate on the CLKIN pin in Hz. If not used,\r
set this to 0. Otherwise, set it to the exact rate in Hz this pin is\r
being driven at. */\r
-static uint32_t s_Ext_Clk_Freq = 16000000U;\r
-static uint32_t s_I2S_Mclk_Freq = 0U;\r
+static uint32_t s_Ext_Clk_Freq = 16000000U;\r
+static uint32_t s_I2S_Mclk_Freq = 0U;\r
+static uint32_t s_PLU_ClkIn_Freq = 0U;\r
\r
/*******************************************************************************\r
* Variables\r
/* Get the greatest common divisor */\r
static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);\r
/* Set PLL output based on desired output rate */\r
-static pll_error_t CLOCK_GetPll0Config(\r
- uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS);\r
+static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS);\r
/* Update local PLL rate variable */\r
static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup);\r
\r
uint8_t mux;\r
uint8_t sel;\r
uint16_t item;\r
+ uint32_t tmp32 = (uint32_t)connection;\r
uint32_t i;\r
volatile uint32_t *pClkSel;\r
\r
pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);\r
\r
- if (connection != kNONE_to_NONE)\r
+ if (kNONE_to_NONE != connection)\r
{\r
for (i = 0U; i < 2U; i++)\r
{\r
- if (connection == 0U)\r
+ if (tmp32 == 0U)\r
{\r
break;\r
}\r
- item = (uint16_t)GET_ID_ITEM(connection);\r
- if (item)\r
+ item = (uint16_t)GET_ID_ITEM(tmp32);\r
+ if (item != 0U)\r
{\r
mux = GET_ID_ITEM_MUX(item);\r
sel = GET_ID_ITEM_SEL(item);\r
pClkSel[mux] = sel;\r
}\r
}\r
- connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */\r
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */\r
}\r
}\r
}\r
{\r
uint8_t mux;\r
uint8_t actualSel;\r
+ uint32_t tmp32 = (uint32_t)attachId;\r
uint32_t i;\r
uint32_t actualAttachId = 0U;\r
- uint32_t selector = GET_ID_SELECTOR(attachId);\r
+ uint32_t selector = GET_ID_SELECTOR(tmp32);\r
volatile uint32_t *pClkSel;\r
\r
pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);\r
\r
- if (attachId == kNONE_to_NONE)\r
+ if (kNONE_to_NONE == attachId)\r
{\r
return kNONE_to_NONE;\r
}\r
\r
for (i = 0U; i < 2U; i++)\r
{\r
- mux = GET_ID_ITEM_MUX(attachId);\r
- if (attachId)\r
+ mux = GET_ID_ITEM_MUX(tmp32);\r
+ if (tmp32 != 0UL)\r
{\r
if (mux == CM_RTCOSC32KCLKSEL)\r
{\r
- actualSel = PMC->RTCOSC32K;\r
+ actualSel = (uint8_t)(PMC->RTCOSC32K);\r
}\r
else\r
{\r
- actualSel = pClkSel[mux];\r
+ actualSel = (uint8_t)(pClkSel[mux]);\r
}\r
\r
/* Consider the combination of two registers */\r
actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);\r
}\r
- attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */\r
+ tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */\r
}\r
\r
actualAttachId |= selector;\r
pClkDiv = &(SYSCON->SYSTICKCLKDIV0);\r
if (reset)\r
{\r
- pClkDiv[div_name] = 1U << 29U;\r
+ pClkDiv[(uint8_t)div_name] = 1UL << 29U;\r
}\r
if (divided_by_value == 0U) /*!< halt */\r
{\r
- pClkDiv[div_name] = 1U << 30U;\r
+ pClkDiv[(uint8_t)div_name] = 1UL << 30U;\r
}\r
else\r
{\r
- pClkDiv[div_name] = (divided_by_value - 1U);\r
+ pClkDiv[(uint8_t)div_name] = (divided_by_value - 1U);\r
}\r
}\r
\r
{\r
if (divided_by_value == 0U) /*!< halt */\r
{\r
- PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT);\r
+ PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT);\r
}\r
else\r
{\r
return kStatus_Fail;\r
}\r
/* Enable Analog Control module */\r
- SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT);\r
+ SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT);\r
SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK;\r
/* Power up the FRO192M */\r
POWER_DisablePD(kPDRUNCFG_PD_FRO192M);\r
{\r
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1);\r
}\r
+ /* always enable\r
else if (iFreq == 48000000U)\r
{\r
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1);\r
- }\r
+ }*/\r
else\r
{\r
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1);\r
}\r
- return 0U;\r
+ return kStatus_Success;\r
}\r
\r
/* Set the FLASH wait states for the passed frequency */\r
/**\r
- * brief Set the flash wait states for the input freuqency.\r
- * param iFreq : Input frequency\r
- * return Nothing\r
+ * brief Set the flash wait states for the input freuqency.\r
+ * param iFreq: Input frequency\r
+ * return Nothing\r
*/\r
void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)\r
{\r
- uint32_t num_wait_states;\r
- float f_num_wait_states = 0.00000009 * ((float)iFreq);\r
- /* Rational : timing is closed at 100MHz+10% tolerance, hence the ¡®9¡¯ in the formula above */\r
- num_wait_states = (uint32_t)f_num_wait_states;\r
+ uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */\r
+\r
+ if (iFreq <= 11000000UL)\r
+ {\r
+ /* [0 - 11 MHz] */\r
+ num_wait_states = 0UL;\r
+ }\r
+ else if (iFreq <= 22000000UL)\r
+ {\r
+ /* [11 MHz - 22 MHz] */\r
+ num_wait_states = 1UL;\r
+ }\r
+ else if (iFreq <= 33000000UL)\r
+ {\r
+ /* [22 MHz - 33 MHz] */\r
+ num_wait_states = 2UL;\r
+ }\r
+ else if (iFreq <= 44000000UL)\r
+ {\r
+ /* [33 MHz - 44 MHz] */\r
+ num_wait_states = 3UL;\r
+ }\r
+ else if (iFreq <= 55000000UL)\r
+ {\r
+ /* [44 MHz - 55 MHz] */\r
+ num_wait_states = 4UL;\r
+ }\r
+ else if (iFreq <= 66000000UL)\r
+ {\r
+ /* [55 MHz - 662 MHz] */\r
+ num_wait_states = 5UL;\r
+ }\r
+ else if (iFreq <= 77000000UL)\r
+ {\r
+ /* [66 MHz - 77 MHz] */\r
+ num_wait_states = 6UL;\r
+ }\r
+ else if (iFreq <= 88000000UL)\r
+ {\r
+ /* [77 MHz - 88 MHz] */\r
+ num_wait_states = 7UL;\r
+ }\r
+ else if (iFreq <= 100000000UL)\r
+ {\r
+ /* [88 MHz - 100 MHz] */\r
+ num_wait_states = 8UL;\r
+ }\r
+ else if (iFreq <= 115000000UL)\r
+ {\r
+ /* [100 MHz - 115 MHz] */\r
+ num_wait_states = 9UL;\r
+ }\r
+ else if (iFreq <= 130000000UL)\r
+ {\r
+ /* [115 MHz - 130 MHz] */\r
+ num_wait_states = 10UL;\r
+ }\r
+ else if (iFreq <= 150000000UL)\r
+ {\r
+ /* [130 MHz - 150 MHz] */\r
+ num_wait_states = 11UL;\r
+ }\r
+ else\r
+ {\r
+ /* Above 150 MHz */\r
+ num_wait_states = 12UL;\r
+ }\r
+\r
+ FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */\r
\r
- /*\r
- * It is guaranteed by design that "num_wait_states = 8"\r
- * will fit all frequencies (below and including) 100 MHz.\r
- */\r
- if (num_wait_states >= 9)\r
+ FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) |\r
+ (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT));\r
+\r
+ FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */\r
+\r
+ /* Wait until the cmd is completed (without error) */\r
+ while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK))\r
{\r
- num_wait_states = 8;\r
+ ;\r
}\r
\r
- /* Don't alter other bits */\r
- SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FMCTIM_MASK) |\r
- ((num_wait_states << SYSCON_FMCCR_FMCTIM_SHIFT) & SYSCON_FMCCR_FMCTIM_MASK);\r
+ /* Adjust FMC waiting time cycles (num_wait_states) */\r
+ SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) |\r
+ ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK);\r
}\r
\r
/* Set EXT OSC Clk */\r
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;\r
\r
s_Ext_Clk_Freq = iFreq;\r
- return 0U;\r
+ return kStatus_Success;\r
}\r
\r
/* Set I2S MCLK Clk */\r
status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq)\r
{\r
s_I2S_Mclk_Freq = iFreq;\r
- return 0U;\r
+ return kStatus_Success;\r
+}\r
+\r
+/* Set PLU CLKIN Clk */\r
+/**\r
+ * brief Initialize the PLU CLKIN clock to given frequency.\r
+ * param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq)\r
+{\r
+ s_PLU_ClkIn_Freq = iFreq;\r
+ return kStatus_Success;\r
}\r
\r
/* Get CLOCK OUT Clk */\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
*/\r
uint32_t CLOCK_GetUsb1ClkFreq(void)\r
{\r
- return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U;\r
+ return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U;\r
}\r
\r
/* Get MCLK Clk */\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
freq = 0U;\r
break;\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
*/\r
uint32_t CLOCK_GetFro12MFreq(void)\r
{\r
- return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
- 0 :\r
- (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;\r
+ return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U;\r
}\r
\r
/* Get FRO 1M Clk */\r
*/\r
uint32_t CLOCK_GetFro1MFreq(void)\r
{\r
- return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;\r
+ return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U;\r
}\r
\r
/* Get EXT OSC Clk */\r
*/\r
uint32_t CLOCK_GetExtClkFreq(void)\r
{\r
- return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U;\r
+ return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U;\r
}\r
\r
/* Get WATCH DOG Clk */\r
*/\r
uint32_t CLOCK_GetFroHfFreq(void)\r
{\r
- return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
- 0 :\r
- (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;\r
+ return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U;\r
}\r
\r
/* Get SYSTEM PLL Clk */\r
*/\r
uint32_t CLOCK_GetOsc32KFreq(void)\r
{\r
- return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?\r
+ return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) &&\r
+ (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?\r
CLK_RTC_32K_CLK :\r
- ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?\r
+ ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) &&\r
+ (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?\r
CLK_RTC_32K_CLK :\r
0U;\r
}\r
}\r
else\r
{\r
+ /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */\r
}\r
break;\r
case 1U:\r
break;\r
\r
default:\r
+ freq = 0U;\r
break;\r
}\r
\r
return s_I2S_Mclk_Freq;\r
}\r
\r
+/* Get PLU CLKIN Clk */\r
+/*! brief Return Frequency of PLU CLKIN Clock\r
+ * return Frequency of PLU CLKIN Clock\r
+ */\r
+uint32_t CLOCK_GetPLUClkInFreq(void)\r
+{\r
+ return s_PLU_ClkIn_Freq;\r
+}\r
+\r
/* Get FLEXCOMM input clock */\r
/*! brief Return Frequency of flexcomm input clock\r
* param id : flexcomm instance id\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)\r
{\r
uint32_t freq = 0U;\r
+ uint32_t temp;\r
\r
freq = CLOCK_GetFlexCommInputClock(id);\r
- return freq / (1 +\r
- (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) /\r
- ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U));\r
+ temp = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK;\r
+ return freq / (1U + (temp) / ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U));\r
}\r
\r
/* Get HS_LPSI Clk */\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
break;\r
\r
default:\r
+ assert(false);\r
break;\r
}\r
\r
{\r
volatile uint32_t *pSystickClkDiv;\r
pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0);\r
- uint32_t freq = 0U;\r
+ uint32_t freq = 0U;\r
\r
switch (SYSCON->SYSTICKCLKSELX[id])\r
{\r
break;\r
\r
default:\r
+ freq = 0U;\r
break;\r
}\r
\r
uint32_t input = CLOCK_GetFlexCommClkFreq(id);\r
uint32_t mul;\r
\r
- if ((freq > 48000000) || (freq > input) || (input / freq >= 2))\r
+ if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL))\r
{\r
/* FRG output frequency should be less than equal to 48MHz */\r
- return 0;\r
+ return 0UL;\r
}\r
else\r
{\r
- mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);\r
+ mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq));\r
SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU;\r
- return 1;\r
+ return 1UL;\r
}\r
}\r
\r
case kCLOCK_ClockOut:\r
freq = CLOCK_GetClockOutClkFreq();\r
break;\r
- case kCLOCK_Adc:\r
- freq = CLOCK_GetAdcClkFreq();\r
- break;\r
- case kCLOCK_Usb0:\r
- freq = CLOCK_GetUsb0ClkFreq();\r
- break;\r
- case kCLOCK_Usb1:\r
- freq = CLOCK_GetUsb1ClkFreq();\r
- break;\r
case kCLOCK_Pll1Out:\r
freq = CLOCK_GetPll1OutFreq();\r
break;\r
case kCLOCK_Pll0Out:\r
freq = CLOCK_GetPll0OutFreq();\r
break;\r
- case kCLOCK_WdtClk:\r
- freq = CLOCK_GetWdtClkFreq();\r
- break;\r
- case kCLOCK_Sct:\r
- freq = CLOCK_GetSctClkFreq();\r
- break;\r
- case kCLOCK_SDio:\r
- freq = CLOCK_GetSdioClkFreq();\r
- break;\r
case kCLOCK_FlexI2S:\r
freq = CLOCK_GetI2SMClkFreq();\r
break;\r
- case kCLOCK_Flexcomm0:\r
- freq = CLOCK_GetFlexCommClkFreq(0U);\r
- break;\r
- case kCLOCK_Flexcomm1:\r
- freq = CLOCK_GetFlexCommClkFreq(1U);\r
- break;\r
- case kCLOCK_Flexcomm2:\r
- freq = CLOCK_GetFlexCommClkFreq(2U);\r
- break;\r
- case kCLOCK_Flexcomm3:\r
- freq = CLOCK_GetFlexCommClkFreq(3U);\r
- break;\r
- case kCLOCK_Flexcomm4:\r
- freq = CLOCK_GetFlexCommClkFreq(4U);\r
- break;\r
- case kCLOCK_Flexcomm5:\r
- freq = CLOCK_GetFlexCommClkFreq(5U);\r
- break;\r
- case kCLOCK_Flexcomm6:\r
- freq = CLOCK_GetFlexCommClkFreq(6U);\r
- break;\r
- case kCLOCK_Flexcomm7:\r
- freq = CLOCK_GetFlexCommClkFreq(7U);\r
- break;\r
- case kCLOCK_HsLspi:\r
- freq = CLOCK_GetHsLspiClkFreq();\r
- break;\r
- case kCLOCK_CTmier0:\r
- freq = CLOCK_GetCTimerClkFreq(0U);\r
- break;\r
- case kCLOCK_CTmier1:\r
- freq = CLOCK_GetCTimerClkFreq(1U);\r
- break;\r
- case kCLOCK_CTmier2:\r
- freq = CLOCK_GetCTimerClkFreq(2U);\r
- break;\r
- case kCLOCK_CTmier3:\r
- freq = CLOCK_GetCTimerClkFreq(3U);\r
- break;\r
- case kCLOCK_CTmier4:\r
- freq = CLOCK_GetCTimerClkFreq(4U);\r
- break;\r
- case kCLOCK_Systick0:\r
- freq = CLOCK_GetSystickClkFreq(0U);\r
- break;\r
- case kCLOCK_Systick1:\r
- freq = CLOCK_GetSystickClkFreq(1U);\r
- break;\r
default:\r
freq = 0U;\r
break;\r
{\r
uint32_t seli, selp;\r
/* bandwidth: compute selP from Multiplier */\r
- if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)\r
+ if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */\r
{\r
selp = (M >> 2U) + 1U;\r
if (selp >= 31U)\r
}\r
*pSelP = selp;\r
\r
- if (M >= 32768)\r
- {\r
- seli = 1;\r
- }\r
- else if (M >= 16384)\r
- {\r
- seli = 2;\r
- }\r
- else if (M >= 4096)\r
+ if (M >= 8000UL)\r
{\r
- seli = 4;\r
+ seli = 1UL;\r
}\r
- else if (M >= 1002)\r
+ else if (M >= 122UL)\r
{\r
- seli = 8;\r
- }\r
- else if (M >= 120)\r
- {\r
- seli = 4 * ((1024/(M/2 + 9)) + 1);\r
+ seli = (uint32_t)(8000UL / M); /*floor(8000/M) */\r
}\r
else\r
{\r
- seli = 4 * (M/8 + 1);\r
- } \r
+ seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */\r
+ }\r
\r
- if (seli >= 63)\r
+ if (seli >= 63UL)\r
{\r
- seli = 63;\r
+ seli = 63UL;\r
}\r
*pSelI = seli;\r
\r
}\r
else\r
{\r
+ /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */\r
*pSelP = 3U;\r
*pSelI = 4U;\r
*pSelR = 4U;\r
/* Get predivider (N) from PLL0 NDEC setting */\r
static uint32_t findPll0PreDiv(void)\r
{\r
- uint32_t preDiv = 1;\r
+ uint32_t preDiv = 1UL;\r
\r
/* Direct input is not used? */\r
- if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL)\r
{\r
preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;\r
- if (preDiv == 0)\r
+ if (preDiv == 0UL)\r
{\r
- preDiv = 1;\r
+ preDiv = 1UL;\r
}\r
}\r
return preDiv;\r
/* Get predivider (N) from PLL1 NDEC setting */\r
static uint32_t findPll1PreDiv(void)\r
{\r
- uint32_t preDiv = 1;\r
+ uint32_t preDiv = 1UL;\r
\r
/* Direct input is not used? */\r
- if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)\r
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL)\r
{\r
preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;\r
- if (preDiv == 0)\r
+ if (preDiv == 0UL)\r
{\r
- preDiv = 1;\r
+ preDiv = 1UL;\r
}\r
}\r
return preDiv;\r
/* Get postdivider (P) from PLL0 PDEC setting */\r
static uint32_t findPll0PostDiv(void)\r
{\r
- uint32_t postDiv = 1;\r
+ uint32_t postDiv = 1UL;\r
\r
- if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL)\r
{\r
- if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL)\r
{\r
postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;\r
}\r
else\r
{\r
- postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);\r
+ postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);\r
}\r
- if (postDiv == 0)\r
+ if (postDiv == 0UL)\r
{\r
- postDiv = 2;\r
+ postDiv = 2UL;\r
}\r
}\r
return postDiv;\r
/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */\r
static float findPll0MMult(void)\r
{\r
- float mMult = 1;\r
+ float mMult = 1.0F;\r
float mMult_fract;\r
uint32_t mMult_int;\r
\r
- if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)\r
+ if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL)\r
{\r
- mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;\r
+ mMult =\r
+ (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT);\r
}\r
else\r
{\r
- mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P);\r
- mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M)/(1 << PLL0_SSCG_MD_INT_P));\r
- mMult = (float)mMult_int + mMult_fract;\r
+ mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U);\r
+ mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P);\r
+ mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) /\r
+ (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P));\r
+ mMult = (float)mMult_int + mMult_fract;\r
}\r
- if (mMult == 0)\r
+ if (mMult == 0.0F)\r
{\r
- mMult = 1;\r
+ mMult = 1.0F;\r
}\r
return mMult;\r
}\r
\r
-\r
/* Find greatest common divisor between m and n */\r
static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)\r
{\r
while (n != 0U)\r
{\r
tmp = n;\r
- n = m % n;\r
- m = tmp;\r
+ n = m % n;\r
+ m = tmp;\r
}\r
\r
return m;\r
* frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.\r
* the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.\r
*/\r
-static pll_error_t CLOCK_GetPll0ConfigInternal(\r
- uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
+static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
{\r
uint32_t nDivOutHz, fccoHz;\r
uint32_t pllPreDivider, pllMultiplier, pllPostDivider;\r
uint32_t pllSelP, pllSelI, pllSelR, uplimoff;\r
\r
/* Baseline parameters (no input or output dividers) */\r
- pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */\r
- pllPostDivider = 1U; /* 1 implies post-divider will be disabled */\r
+ pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */\r
+ pllPostDivider = 1U; /* 1 implies post-divider will be disabled */\r
pllDirectOutput = 1U;\r
\r
/* Verify output rate parameter */\r
\r
/* Target CCO goes up, PLL output goes down */\r
/* divide-by-2 divider in the post-divider is always work*/\r
- fccoHz = foutHz * (pllPostDivider * 2U);\r
+ fccoHz = foutHz * (pllPostDivider * 2U);\r
pllDirectOutput = 0U;\r
}\r
\r
}\r
\r
/* Determine PLL multipler */\r
- nDivOutHz = (finHz / pllPreDivider);\r
+ nDivOutHz = (finHz / pllPreDivider);\r
pllMultiplier = (fccoHz / nDivOutHz);\r
\r
/* Find optimal values for filter */\r
uplimoff = 0U;\r
\r
/* Get encoded value for M (mult) and use manual filter, disable SS mode */\r
- pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT);\r
+ pSetup->pllsscg[1] =\r
+ (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT));\r
}\r
else\r
{\r
uint64_t fc;\r
\r
/* Filtering will be handled by SSC */\r
- pllSelR = pllSelI = pllSelP = 0U;\r
+ pllSelR = 0U;\r
+ pllSelI = 0U;\r
+ pllSelP = 0U;\r
uplimoff = 1U;\r
\r
/* The PLL multiplier will get very close and slightly under the\r
desired target frequency. A small fractional component can be\r
added to fine tune the frequency upwards to the target. */\r
- fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz;\r
+ fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz;\r
\r
/* Set multiplier */\r
pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc));\r
- pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U;\r
+ pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U);\r
}\r
\r
/* Get encoded values for N (prediv) and P (postdiv) */\r
pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider);\r
\r
/* PLL control */\r
- pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */\r
- (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */\r
- (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */\r
- (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */\r
- (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */\r
- (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */\r
- (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */\r
- (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */\r
+ pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */\r
+ (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */\r
+ (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */\r
+ (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */\r
+ (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */\r
+ (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */\r
+ (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */\r
+ (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */\r
\r
return kStatus_PLL_Success;\r
}\r
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
/* Alloct the static buffer for cache. */\r
static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];\r
-static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
+static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
-static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};\r
-static uint32_t s_PllSetupCacheIdx = 0U;\r
+static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};\r
+static uint32_t s_PllSetupCacheIdx = 0U;\r
#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
\r
/*\r
* Calculate the PLL setting values from input clock freq to output freq.\r
*/\r
-static pll_error_t CLOCK_GetPll0Config(\r
- uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
+static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
{\r
pll_error_t retErr;\r
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i]))\r
{\r
/* Hit the target in cache buffer. */\r
- pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl;\r
- pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec;\r
- pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec;\r
+ pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl;\r
+ pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec;\r
+ pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec;\r
pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0];\r
pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1];\r
- retErr = kStatus_PLL_Success;\r
+ retErr = kStatus_PLL_Success;\r
break;\r
}\r
}\r
\r
#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
/* Cache the most recent calulation result into buffer. */\r
- s_FinHzCache[s_PllSetupCacheIdx] = finHz;\r
+ s_FinHzCache[s_PllSetupCacheIdx] = finHz;\r
s_FoutHzCache[s_PllSetupCacheIdx] = foutHz;\r
- s_UseSSCache[s_PllSetupCacheIdx] = useSS;\r
+ s_UseSSCache[s_PllSetupCacheIdx] = useSS;\r
\r
- s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl;\r
- s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec;\r
- s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec;\r
s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0];\r
s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1];\r
/* Update the index for next available buffer. */\r
\r
/* Return System PLL input clock rate */\r
/*! brief Return PLL0 input clock rate\r
-* return PLL0 input clock rate\r
-*/\r
+ * return PLL0 input clock rate\r
+ */\r
uint32_t CLOCK_GetPLL0InClockRate(void)\r
{\r
uint32_t clkRate = 0U;\r
\r
/* Return PLL0 output clock rate from setup structure */\r
/*! brief Return PLL0 output clock rate from setup structure\r
-* param pSetup : Pointer to a PLL setup structure\r
-* return PLL0 output clock rate the setup structure will generate\r
-*/\r
+ * param pSetup : Pointer to a PLL setup structure\r
+ * return PLL0 output clock rate the setup structure will generate\r
+ */\r
uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)\r
{\r
uint32_t clkRate = 0;\r
uint32_t prediv, postdiv;\r
- float workRate = 0;\r
+ float workRate = 0.0F;\r
\r
/* Get the input clock frequency of PLL. */\r
clkRate = CLOCK_GetPLL0InClockRate();\r
\r
- if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))\r
+ if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&\r
+ ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&\r
+ ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) &&\r
+ ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL))\r
{\r
- prediv = findPll0PreDiv();\r
+ prediv = findPll0PreDiv();\r
postdiv = findPll0PostDiv();\r
/* Adjust input clock */\r
clkRate = clkRate / prediv;\r
/* MDEC used for rate */\r
workRate = (float)clkRate * (float)findPll0MMult();\r
- clkRate = (uint32_t)(workRate / ((float)postdiv));\r
+ workRate /= (float)postdiv;\r
}\r
\r
return (uint32_t)workRate;\r
\r
/* Set the current PLL0 Rate */\r
/*! brief Store the current PLL rate\r
-* param rate: Current rate of the PLL\r
-* return Nothing\r
-**/\r
+ * param rate: Current rate of the PLL\r
+ * return Nothing\r
+ **/\r
void CLOCK_SetStoredPLL0ClockRate(uint32_t rate)\r
{\r
s_Pll0_Freq = rate;\r
\r
/* Return PLL0 output clock rate */\r
/*! brief Return PLL0 output clock rate\r
-* param recompute : Forces a PLL rate recomputation if true\r
-* return PLL0 output clock rate\r
-* note The PLL rate is cached in the driver in a variable as\r
-* the rate computation function can take some time to perform. It\r
-* is recommended to use 'false' with the 'recompute' parameter.\r
-*/\r
+ * param recompute : Forces a PLL rate recomputation if true\r
+ * return PLL0 output clock rate\r
+ * note The PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
uint32_t CLOCK_GetPLL0OutClockRate(bool recompute)\r
{\r
pll_setup_t Setup;\r
\r
if ((recompute) || (s_Pll0_Freq == 0U))\r
{\r
- Setup.pllctrl = SYSCON->PLL0CTRL;\r
- Setup.pllndec = SYSCON->PLL0NDEC;\r
- Setup.pllpdec = SYSCON->PLL0PDEC;\r
+ Setup.pllctrl = SYSCON->PLL0CTRL;\r
+ Setup.pllndec = SYSCON->PLL0NDEC;\r
+ Setup.pllpdec = SYSCON->PLL0PDEC;\r
Setup.pllsscg[0] = SYSCON->PLL0SSCG0;\r
Setup.pllsscg[1] = SYSCON->PLL0SSCG1;\r
\r
\r
/* Set PLL0 output based on the passed PLL setup data */\r
/*! brief Set PLL output based on the passed PLL setup data\r
-* param pControl : Pointer to populated PLL control structure to generate setup with\r
-* param pSetup : Pointer to PLL setup structure to be filled\r
-* return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
-* note Actual frequency for setup may vary from the desired frequency based on the\r
-* accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
-*/\r
+ * param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * param pSetup : Pointer to PLL setup structure to be filled\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup)\r
{\r
uint32_t inRate;\r
- bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U);\r
+ bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U);\r
\r
pll_error_t pllError;\r
\r
pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc;\r
if (pControl->mfDither)\r
{\r
- pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT);\r
+ pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT);\r
}\r
}\r
\r
\r
/* Set PLL0 output from PLL setup structure */\r
/*! brief Set PLL output from PLL setup structure (precise frequency)\r
-* param pSetup : Pointer to populated PLL setup structure\r
-* param flagcfg : Flag configuration for PLL config structure\r
-* return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
-* note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * param flagcfg : Flag configuration for PLL config structure\r
+ * return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg)\r
-{ \r
+{\r
uint32_t inRate, clkRate, prediv;\r
\r
/* Power off PLL during setup changes */\r
pSetup->flags = flagcfg;\r
\r
/* Write PLL setup data */\r
- SYSCON->PLL0CTRL = pSetup->pllctrl;\r
- SYSCON->PLL0NDEC = pSetup->pllndec;\r
- SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
- SYSCON->PLL0PDEC = pSetup->pllpdec;\r
- SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0CTRL = pSetup->pllctrl;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec;\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];\r
SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];\r
SYSCON->PLL0SSCG1 =\r
- pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */\r
+ pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */\r
\r
POWER_DisablePD(kPDRUNCFG_PD_PLL0);\r
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
\r
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
{\r
- inRate = CLOCK_GetPLL0InClockRate();\r
- prediv = findPll0PreDiv();\r
- /* Adjust input clock */\r
- clkRate = inRate / prediv;\r
- /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
- if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */\r
{\r
- while (CLOCK_IsPLL0Locked() == false)\r
+ inRate = CLOCK_GetPLL0InClockRate();\r
+ prediv = findPll0PreDiv();\r
+ /* Adjust input clock */\r
+ clkRate = inRate / prediv;\r
+ /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
+ if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))\r
+ {\r
+ while (CLOCK_IsPLL0Locked() == false)\r
+ {\r
+ }\r
+ }\r
+ else\r
{\r
+ SDK_DelayAtLeastUs(6000U,\r
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval\r
+ to insure the PLL will be stable */\r
}\r
}\r
+ else /* spread spectrum mode */\r
+ {\r
+ SDK_DelayAtLeastUs(6000U,\r
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to\r
+ insure the PLL will be stable */\r
+ }\r
}\r
\r
/* Update current programmed PLL rate var */\r
\r
/* Setup PLL Frequency from pre-calculated value */\r
/**\r
-* brief Set PLL0 output from PLL setup structure (precise frequency)\r
-* param pSetup : Pointer to populated PLL setup structure\r
-* return kStatus_PLL_Success on success, or PLL setup error code\r
-* note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * brief Set PLL0 output from PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * return kStatus_PLL_Success on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup)\r
{\r
uint32_t inRate, clkRate, prediv;\r
POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
\r
/* Write PLL setup data */\r
- SYSCON->PLL0CTRL = pSetup->pllctrl;\r
- SYSCON->PLL0NDEC = pSetup->pllndec;\r
- SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
- SYSCON->PLL0PDEC = pSetup->pllpdec;\r
- SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0CTRL = pSetup->pllctrl;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec;\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];\r
SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];\r
SYSCON->PLL0SSCG1 =\r
- pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */\r
+ pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */\r
\r
POWER_DisablePD(kPDRUNCFG_PD_PLL0);\r
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
\r
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
{\r
- inRate = CLOCK_GetPLL0InClockRate();\r
- prediv = findPll0PreDiv();\r
- /* Adjust input clock */\r
- clkRate = inRate / prediv;\r
- /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
- if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */\r
{\r
- while (CLOCK_IsPLL0Locked() == false)\r
+ inRate = CLOCK_GetPLL0InClockRate();\r
+ prediv = findPll0PreDiv();\r
+ /* Adjust input clock */\r
+ clkRate = inRate / prediv;\r
+ /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
+ if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))\r
+ {\r
+ while (CLOCK_IsPLL0Locked() == false)\r
+ {\r
+ }\r
+ }\r
+ else\r
{\r
+ SDK_DelayAtLeastUs(6000U,\r
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval\r
+ to insure the PLL will be stable */\r
}\r
}\r
+ else /* spread spectrum mode */\r
+ {\r
+ SDK_DelayAtLeastUs(6000U,\r
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to\r
+ insure the PLL will be stable */\r
+ }\r
}\r
\r
/* Update current programmed PLL rate var */\r
\r
/* Setup PLL1 Frequency from pre-calculated value */\r
/**\r
-* brief Set PLL1 output from PLL setup structure (precise frequency)\r
-* param pSetup : Pointer to populated PLL setup structure\r
-* return kStatus_PLL_Success on success, or PLL setup error code\r
-* note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * brief Set PLL1 output from PLL setup structure (precise frequency)\r
+ * param pSetup : Pointer to populated PLL setup structure\r
+ * return kStatus_PLL_Success on success, or PLL setup error code\r
+ * note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)\r
{\r
uint32_t inRate, clkRate, prediv;\r
/* Write PLL setup data */\r
SYSCON->PLL1CTRL = pSetup->pllctrl;\r
SYSCON->PLL1NDEC = pSetup->pllndec;\r
- SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */\r
SYSCON->PLL1PDEC = pSetup->pllpdec;\r
- SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */\r
SYSCON->PLL1MDEC = pSetup->pllmdec;\r
- SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */\r
+ SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */\r
\r
POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
\r
/* Adjust input clock */\r
clkRate = inRate / prediv;\r
/* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
- if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ if ((clkRate >= 100000UL) && (clkRate <= 20000000UL))\r
{\r
while (CLOCK_IsPLL1Locked() == false)\r
{\r
}\r
}\r
+ else\r
+ {\r
+ SDK_DelayAtLeastUs(6000U,\r
+ SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to\r
+ insure the PLL will be stable */\r
+ }\r
}\r
\r
/* Update current programmed PLL rate var */\r
\r
/* Set PLL0 clock based on the input frequency and multiplier */\r
/*! brief Set PLL0 output based on the multiplier and input frequency\r
-* param multiply_by : multiplier\r
-* param input_freq : Clock input frequency of the PLL\r
-* return Nothing\r
-* note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
-* function does not disable or enable PLL power, wait for PLL lock,\r
-* or adjust system voltages. These must be done in the application.\r
-* The function will not alter any source clocks (ie, main systen clock)\r
-* that may use the PLL, so these should be setup prior to and after\r
-* exiting the function.\r
-*/\r
+ * param multiply_by : multiplier\r
+ * param input_freq : Clock input frequency of the PLL\r
+ * return Nothing\r
+ * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+ * function does not disable or enable PLL power, wait for PLL lock,\r
+ * or adjust system voltages. These must be done in the application.\r
+ * The function will not alter any source clocks (ie, main systen clock)\r
+ * that may use the PLL, so these should be setup prior to and after\r
+ * exiting the function.\r
+ */\r
void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq)\r
{\r
uint32_t cco_freq = input_freq * multiply_by;\r
- uint32_t pdec = 1U;\r
+ uint32_t pdec = 1U;\r
uint32_t selr;\r
uint32_t seli;\r
uint32_t selp;\r
\r
selr = 0U;\r
\r
- if (multiply_by >= 32768)\r
- {\r
- seli = 1;\r
- }\r
- else if (multiply_by >= 16384)\r
- {\r
- seli = 2;\r
- }\r
- else if (multiply_by >= 4096)\r
- {\r
- seli = 4;\r
- }\r
- else if (multiply_by >= 1002)\r
+ if (multiply_by >= 8000UL)\r
{\r
- seli = 8;\r
+ seli = 1UL;\r
}\r
- else if (multiply_by >= 120)\r
+ else if (multiply_by >= 122UL)\r
{\r
- seli = 4 * ((1024/(multiply_by/2 + 9)) + 1);\r
+ seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */\r
}\r
else\r
{\r
- seli = 4 * (multiply_by/8 + 1);\r
- } \r
+ seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */\r
+ }\r
\r
if (seli >= 63U)\r
{\r
seli = 63U;\r
}\r
- selp = (multiply_by >> 2U) + 1U;\r
+\r
{\r
selp = 31U;\r
}\r
/* Translate P value */\r
}\r
\r
- mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by);\r
+ mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by);\r
ndec = 0x1U; /* pre divide by 1 (hardcoded) */\r
\r
- SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK |SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) |\r
- (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | (seli << SYSCON_PLL0CTRL_SELI_SHIFT) |\r
- (selp << SYSCON_PLL0CTRL_SELP_SHIFT);\r
- SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */\r
- SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */\r
- SYSCON->PLL0SSCG1 = mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */\r
+ SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) |\r
+ SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) |\r
+ (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT);\r
+ SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */\r
+ SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */\r
+ SYSCON->PLL0SSCG1 =\r
+ mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */\r
}\r
\r
/* Enable USB DEVICE FULL SPEED clock */\r
/*! brief Enable USB Device FS clock.\r
-* param src : clock source\r
-* param freq: clock frequency\r
-* Enable USB Device Full Speed clock.\r
-*/\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB Device Full Speed clock.\r
+ */\r
bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)\r
{\r
bool ret = true;\r
}\r
else\r
{\r
- /*Set the USB PLL as the Usb0 CLK*/\r
- POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
- POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */\r
- POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */\r
- SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */\r
- ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;\r
-\r
- CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */\r
+ /*!< Configure XTAL32M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */\r
+ (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */\r
\r
+ /*!< Set up PLL1 */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */\r
const pll_setup_t pll1Setup = {\r
- .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),\r
+ .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U),\r
.pllndec = SYSCON_PLL1NDEC_NDIV(1U),\r
- .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),\r
- .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),\r
+ .pllpdec = SYSCON_PLL1PDEC_PDIV(5U),\r
+ .pllmdec = SYSCON_PLL1MDEC_MDIV(30U),\r
.pllRate = 48000000U,\r
- .flags = PLL_SETUPFLAG_WAITLOCK,\r
- };\r
-\r
- CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */\r
+ .flags = PLL_SETUPFLAG_WAITLOCK};\r
+ (void)CLOCK_SetPLL1Freq(&pll1Setup);\r
\r
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
CLOCK_AttachClk(kPLL1_to_USB0_CLK);\r
- uint32_t delay = 100000;\r
- while (delay--)\r
- {\r
- __asm("nop");\r
- }\r
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
}\r
CLOCK_EnableClock(kCLOCK_Usbd0);\r
CLOCK_EnableClock(kCLOCK_UsbRam1);\r
\r
/* Enable USB HOST FULL SPEED clock */\r
/*! brief Enable USB HOST FS clock.\r
-* param src : clock source\r
-* param freq: clock frequency\r
-* Enable USB HOST Full Speed clock.\r
-*/\r
+ * param src : clock source\r
+ * param freq: clock frequency\r
+ * Enable USB HOST Full Speed clock.\r
+ */\r
bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)\r
{\r
bool ret = true;\r
}\r
else\r
{\r
- /*Set the USB PLL as the Usb0 CLK*/\r
- POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
- POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */\r
- POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */\r
- SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */\r
- ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;\r
-\r
- CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */\r
+ /*!< Configure XTAL32M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */\r
+ (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */\r
\r
+ /*!< Set up PLL1 */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */\r
const pll_setup_t pll1Setup = {\r
- .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),\r
+ .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U),\r
.pllndec = SYSCON_PLL1NDEC_NDIV(1U),\r
- .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),\r
- .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),\r
+ .pllpdec = SYSCON_PLL1PDEC_PDIV(5U),\r
+ .pllmdec = SYSCON_PLL1MDEC_MDIV(30U),\r
.pllRate = 48000000U,\r
- .flags = PLL_SETUPFLAG_WAITLOCK,\r
- };\r
-\r
- CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */\r
+ .flags = PLL_SETUPFLAG_WAITLOCK};\r
+ (void)CLOCK_SetPLL1Freq(&pll1Setup);\r
\r
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
CLOCK_AttachClk(kPLL1_to_USB0_CLK);\r
- uint32_t delay = 100000;\r
- while (delay--)\r
- {\r
- __asm("nop");\r
- }\r
+ SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);\r
}\r
CLOCK_EnableClock(kCLOCK_Usbhmr0);\r
CLOCK_EnableClock(kCLOCK_Usbhsl0);\r
POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */\r
\r
/* wait to make sure PHY power is fully up */\r
- i = 100000;\r
- while (i--)\r
+ i = 100000U;\r
+ while ((i--) != 0U)\r
{\r
- __asm("nop");\r
+ __ASM("nop");\r
}\r
\r
SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1);\r
SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1);\r
\r
- USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;\r
- USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);\r
+ USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;\r
+ USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);\r
USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;\r
- USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK;\r
+ USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0\r
USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;\r
USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;\r
- USBPHY->PLL_SIC_SET =\r
- USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */\r
\r
USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;\r
- USBPHY->PWD_SET = 0x0;\r
+ USBPHY->PWD_SET = 0x0;\r
\r
return true;\r
}\r
projects / freertos / blobdiff