/*\r
- * Copyright (c) 2017 - 2018 , NXP\r
+ * Copyright 2017 - 2019 , NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
#ifndef _FSL_CLOCK_H_\r
#define _FSL_CLOCK_H_\r
\r
-#include "fsl_device_registers.h"\r
-#include <stdint.h>\r
-#include <stdbool.h>\r
-#include <assert.h>\r
+#include "fsl_common.h"\r
\r
/*! @addtogroup clock */\r
/*! @{ */\r
\r
/*! @name Driver version */\r
/*@{*/\r
-/*! @brief CLOCK driver version 2.0.3. */\r
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))\r
+/*! @brief CLOCK driver version 2.3.1. */\r
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))\r
/*@}*/\r
\r
/*! @brief Configure whether driver controls clock\r
#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U\r
#endif\r
\r
+/* Definition for delay API in clock driver, users can redefine it to the real application. */\r
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY\r
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL)\r
+#endif\r
+\r
/*! @brief Clock ip name array for ROM. */\r
#define ROM_CLOCKS \\r
{ \\r
kCLOCK_Fmc \\r
}\r
/*! @brief Clock ip name array for INPUTMUX. */\r
-#define INPUTMUX_CLOCKS \\r
- { \\r
- kCLOCK_InputMux0, kCLOCK_InputMux1 \\r
+#define INPUTMUX_CLOCKS \\r
+ { \\r
+ kCLOCK_InputMux0 \\r
}\r
/*! @brief Clock ip name array for IOCON. */\r
#define IOCON_CLOCKS \\r
kCLOCK_Iocon \\r
}\r
/*! @brief Clock ip name array for GPIO. */\r
-#define GPIO_CLOCKS \\r
- { \\r
- kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \\r
+#define GPIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \\r
}\r
/*! @brief Clock ip name array for PINT. */\r
#define PINT_CLOCKS \\r
kCLOCK_Pint \\r
}\r
/*! @brief Clock ip name array for GINT. */\r
-#define GINT_CLOCKS \\r
- { \\r
+#define GINT_CLOCKS \\r
+ { \\r
kCLOCK_Gint, kCLOCK_Gint \\r
}\r
/*! @brief Clock ip name array for DMA. */\r
{ \\r
kCLOCK_Sct0 \\r
}\r
-/*! @brief Clock ip name array for SCTIPU. */\r
-#define SCTIPU_CLOCKS \\r
- { \\r
- kCLOCK_Sctipu \\r
- }\r
/*! @brief Clock ip name array for UTICK. */\r
#define UTICK_CLOCKS \\r
{ \\r
kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \\r
kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \\r
}\r
-/*! @brief Clock ip name array for USBTYPC. */\r
-#define USBTYPC_CLOCKS \\r
- { \\r
- kCLOCK_UsbTypc \\r
- }\r
/*! @brief Clock ip name array for CTIMER. */\r
#define CTIMER_CLOCKS \\r
{ \\r
kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \\r
}\r
-/*! @brief Clock ip name array for PVT */\r
-#define PVT_CLOCKS \\r
- { \\r
- kCLOCK_Pvt \\r
- }\r
-/*! @brief Clock ip name array for EZHA */\r
-#define EZHA_CLOCKS \\r
- { \\r
- kCLOCK_Ezha \\r
- }\r
-/*! @brief Clock ip name array for EZHB */\r
-#define EZHB_CLOCKS \\r
- { \\r
- kCLOCK_Ezhb \\r
- }\r
/*! @brief Clock ip name array for COMP */\r
#define COMP_CLOCKS \\r
{ \\r
{ \\r
kCLOCK_UsbRam1 \\r
}\r
-/*! @brief Clock ip name array for OTP. */\r
-#define OTP_CLOCKS \\r
- { \\r
- kCLOCK_Otp \\r
- }\r
/*! @brief Clock ip name array for RNG. */\r
#define RNG_CLOCKS \\r
{ \\r
{ \\r
kCLOCK_PluLut \\r
}\r
-#define SYSCTL_CLOCKS \\r
+#define SYSCTL_CLOCKS \\r
{ \\r
kCLOCK_Sysctl \\r
}\r
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
typedef enum _clock_ip_name\r
{\r
- kCLOCK_IpInvalid = 0U,\r
- kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),\r
- kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),\r
- kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),\r
- kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),\r
- kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),\r
- kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),\r
- kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),\r
- kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),\r
- kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),\r
- kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),\r
- kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),\r
- kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),\r
- kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),\r
- kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),\r
- kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),\r
- kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),\r
- kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),\r
- kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),\r
- kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),\r
- kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),\r
- kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),\r
- kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),\r
- kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),\r
- kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),\r
- kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),\r
- kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),\r
- kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
- kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
- kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
- kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
- kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
- kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
- kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
- kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
- kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
- kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
- kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
- kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
- kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
- kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
- kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
- kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
- kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
- kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
- kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
- kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
- kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
- kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
- kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
- kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
- kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
- kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
- kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
- kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
- kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
- kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
- kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
- kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
- kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
- kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
- kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
- kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
- kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
- kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
- kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
- kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
- kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20),\r
- kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),\r
- kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),\r
- kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),\r
- kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),\r
- kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),\r
- kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),\r
- kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),\r
- kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),\r
- kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),\r
- kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),\r
- kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),\r
- kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),\r
- kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),\r
- kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),\r
- kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),\r
- kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),\r
- kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),\r
- kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),\r
- kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),\r
- kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
- kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), \r
- kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),\r
- kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),\r
- kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),\r
- kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),\r
- kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),\r
- kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),\r
- kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),\r
- kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),\r
- kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),\r
- kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),\r
- kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),\r
- kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),\r
- kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)\r
+ kCLOCK_IpInvalid = 0U,\r
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),\r
+ kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),\r
+ kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),\r
+ kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),\r
+ kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),\r
+ kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),\r
+ kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),\r
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),\r
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),\r
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),\r
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),\r
+ kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),\r
+ kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),\r
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),\r
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),\r
+ kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),\r
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),\r
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),\r
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),\r
+ kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),\r
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),\r
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),\r
+ kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),\r
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),\r
+ kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),\r
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),\r
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),\r
+ kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),\r
+ kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),\r
+ kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),\r
+ kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),\r
+ kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),\r
+ kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),\r
+ kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),\r
+ kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),\r
+ kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),\r
+ kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),\r
+ kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),\r
+ kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),\r
+ kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),\r
+ kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),\r
+ kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),\r
+ kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),\r
+ kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),\r
+ kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),\r
+ kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),\r
+ kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),\r
+ kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),\r
+ kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),\r
+ kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),\r
+ kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),\r
+ kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),\r
+ kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),\r
+ kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),\r
+ kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)\r
} clock_ip_name_t;\r
\r
/*! @brief Peripherals clock source definition. */\r
kCLOCK_BusClk, /*!< Bus clock (AHB clock) */\r
kCLOCK_ClockOut, /*!< CLOCKOUT */\r
kCLOCK_FroHf, /*!< FRO48/96 */\r
- kCLOCK_Adc, /*!< ADC */\r
- kCLOCK_Usb0, /*!< USB0 */\r
- kCLOCK_Usb1, /*!< USB1 */\r
kCLOCK_Pll1Out, /*!< PLL1 Output */\r
kCLOCK_Mclk, /*!< MCLK */\r
- kCLOCK_Sct, /*!< SCT */\r
- kCLOCK_SDio, /*!< SDIO */\r
kCLOCK_Fro12M, /*!< FRO12M */\r
kCLOCK_ExtClk, /*!< External Clock */\r
kCLOCK_Pll0Out, /*!< PLL0 Output */\r
- kCLOCK_WdtClk, /*!< Watchdog clock */\r
kCLOCK_FlexI2S, /*!< FlexI2S clock */\r
- kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */\r
- kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */\r
- kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */\r
- kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */\r
- kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */\r
- kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */\r
- kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */\r
- kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */\r
- kCLOCK_HsLspi, /*!< HS LPSPI Clock */\r
- kCLOCK_CTmier0, /*!< CTmier0Clock */\r
- kCLOCK_CTmier1, /*!< CTmier1Clock */\r
- kCLOCK_CTmier2, /*!< CTmier2Clock */\r
- kCLOCK_CTmier3, /*!< CTmier3Clock */\r
- kCLOCK_CTmier4, /*!< CTmier4Clock */\r
- kCLOCK_Systick0, /*!< System Tick 0 Clock */\r
- kCLOCK_Systick1, /*!< System Tick 1 Clock */\r
\r
} clock_name_t;\r
\r
/*! @brief Clock Mux Switches\r
-* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable\r
-* starting from LSB upwards\r
-*\r
-* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*\r
-*\r
-*/\r
+ * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable\r
+ * starting from LSB upwards\r
+ *\r
+ * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*\r
+ *\r
+ */\r
\r
-#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U))\r
-#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U)\r
-#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U))\r
+#define CLK_ATTACH_ID(mux, sel, pos) \\r
+ ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))\r
+#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)\r
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))\r
\r
#define GET_ID_ITEM(connection) ((connection)&0xFFFU)\r
#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)\r
-#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU)\r
-#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U)\r
+#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)\r
+#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))\r
#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)\r
\r
-#define CM_SYSTICKCLKSEL0 0\r
-#define CM_SYSTICKCLKSEL1 1\r
-#define CM_TRACECLKSEL 2\r
-#define CM_CTIMERCLKSEL0 3\r
-#define CM_CTIMERCLKSEL1 4\r
-#define CM_CTIMERCLKSEL2 5\r
-#define CM_CTIMERCLKSEL3 6\r
-#define CM_CTIMERCLKSEL4 7\r
-#define CM_MAINCLKSELA 8\r
-#define CM_MAINCLKSELB 9\r
-#define CM_CLKOUTCLKSEL 10\r
-#define CM_PLL0CLKSEL 12\r
-#define CM_PLL1CLKSEL 13\r
-#define CM_ADCASYNCCLKSEL 17\r
-#define CM_USB0CLKSEL 18\r
-#define CM_FXCOMCLKSEL0 20\r
-#define CM_FXCOMCLKSEL1 21\r
-#define CM_FXCOMCLKSEL2 22\r
-#define CM_FXCOMCLKSEL3 23\r
-#define CM_FXCOMCLKSEL4 24\r
-#define CM_FXCOMCLKSEL5 25\r
-#define CM_FXCOMCLKSEL6 26\r
-#define CM_FXCOMCLKSEL7 27\r
-#define CM_HSLSPICLKSEL 28\r
-#define CM_MCLKCLKSEL 32\r
-#define CM_SCTCLKSEL 36\r
-#define CM_SDIOCLKSEL 38\r
-\r
-#define CM_RTCOSC32KCLKSEL 63\r
+#define CM_SYSTICKCLKSEL0 0U\r
+#define CM_SYSTICKCLKSEL1 1U\r
+#define CM_TRACECLKSEL 2U\r
+#define CM_CTIMERCLKSEL0 3U\r
+#define CM_CTIMERCLKSEL1 4U\r
+#define CM_CTIMERCLKSEL2 5U\r
+#define CM_CTIMERCLKSEL3 6U\r
+#define CM_CTIMERCLKSEL4 7U\r
+#define CM_MAINCLKSELA 8U\r
+#define CM_MAINCLKSELB 9U\r
+#define CM_CLKOUTCLKSEL 10U\r
+#define CM_PLL0CLKSEL 12U\r
+#define CM_PLL1CLKSEL 13U\r
+#define CM_ADCASYNCCLKSEL 17U\r
+#define CM_USB0CLKSEL 18U\r
+#define CM_FXCOMCLKSEL0 20U\r
+#define CM_FXCOMCLKSEL1 21U\r
+#define CM_FXCOMCLKSEL2 22U\r
+#define CM_FXCOMCLKSEL3 23U\r
+#define CM_FXCOMCLKSEL4 24U\r
+#define CM_FXCOMCLKSEL5 25U\r
+#define CM_FXCOMCLKSEL6 26U\r
+#define CM_FXCOMCLKSEL7 27U\r
+#define CM_HSLSPICLKSEL 28U\r
+#define CM_MCLKCLKSEL 32U\r
+#define CM_SCTCLKSEL 36U\r
+#define CM_SDIOCLKSEL 38U\r
+\r
+#define CM_RTCOSC32KCLKSEL 63U\r
\r
typedef enum _clock_attach_id\r
{\r
\r
- kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
- kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
- kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
- kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),\r
- kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),\r
- kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),\r
+ kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),\r
+ kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),\r
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),\r
\r
kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),\r
- kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),\r
- kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),\r
- kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),\r
- kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),\r
- kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),\r
- kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),\r
+ kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),\r
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),\r
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),\r
+ kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),\r
+ kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),\r
+ kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),\r
kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),\r
\r
- kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),\r
+ kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),\r
kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),\r
- kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),\r
- kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),\r
- kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),\r
+ kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),\r
+ kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),\r
+ kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),\r
\r
kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),\r
- kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),\r
- kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),\r
- kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */\r
- kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),\r
+ kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),\r
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),\r
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),\r
\r
kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),\r
- kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),\r
- kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),\r
- kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),\r
- kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),\r
- kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),\r
- kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),\r
+ kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),\r
+ kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),\r
+ kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),\r
+ kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),\r
+ kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),\r
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),\r
kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),\r
- kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),\r
- kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),\r
- kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),\r
- kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),\r
- kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),\r
- kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),\r
+ kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),\r
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),\r
+ kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),\r
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),\r
+ kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),\r
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),\r
kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),\r
- kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),\r
- kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),\r
- kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),\r
- kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),\r
- kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),\r
- kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),\r
+ kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),\r
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),\r
+ kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),\r
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),\r
+ kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),\r
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),\r
kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),\r
- kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),\r
- kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),\r
- kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),\r
- kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),\r
- kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),\r
- kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),\r
+ kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),\r
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),\r
+ kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),\r
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),\r
+ kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),\r
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),\r
kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),\r
- kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),\r
- kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),\r
- kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),\r
- kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),\r
- kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),\r
- kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),\r
+ kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),\r
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),\r
+ kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),\r
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),\r
+ kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),\r
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),\r
kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),\r
- kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),\r
- kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),\r
- kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),\r
- kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),\r
- kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),\r
- kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),\r
+ kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),\r
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),\r
+ kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),\r
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),\r
+ kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),\r
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),\r
kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),\r
- kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),\r
- kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),\r
- kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),\r
- kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),\r
- kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),\r
- kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),\r
+ kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),\r
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),\r
+ kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),\r
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),\r
+ kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),\r
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),\r
kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),\r
- kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),\r
- kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),\r
- kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),\r
- kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),\r
-\r
- kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),\r
- kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),\r
- kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),\r
+ kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),\r
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),\r
+ kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),\r
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),\r
+ kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),\r
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),\r
kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),\r
- kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),\r
- kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),\r
- kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),\r
- kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),\r
-\r
- kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),\r
- kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),\r
- kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),\r
+ kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),\r
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),\r
+ kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),\r
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),\r
+\r
+ kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),\r
+ kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),\r
+ kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),\r
kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),\r
- kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),\r
- kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),\r
- kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),\r
+ kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),\r
+ kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),\r
+ kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),\r
\r
kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),\r
- kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),\r
- kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */\r
- kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */\r
- kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),\r
+ kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),\r
+ kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),\r
\r
kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),\r
- kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),\r
- kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),\r
- kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),\r
- kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),\r
- kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),\r
+ kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),\r
+ kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),\r
+ kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),\r
+ kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),\r
+ kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),\r
\r
kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),\r
- kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),\r
- kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),\r
- kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),\r
- kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),\r
+ kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),\r
+ kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),\r
+ kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),\r
+ kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),\r
\r
- kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),\r
+ kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),\r
kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),\r
\r
kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),\r
- kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),\r
- kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),\r
- kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),\r
+ kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),\r
+ kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),\r
+ kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),\r
\r
kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),\r
- kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),\r
- kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),\r
- kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),\r
+ kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),\r
+ kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),\r
+ kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),\r
\r
kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),\r
- kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),\r
- kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),\r
- kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),\r
+ kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),\r
+ kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),\r
+ kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),\r
\r
- kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),\r
+ kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),\r
kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),\r
- kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),\r
- kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),\r
- kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),\r
+ kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),\r
+ kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),\r
+ kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),\r
\r
kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),\r
- kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),\r
- kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),\r
- kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),\r
- kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),\r
- kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),\r
- kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),\r
+ kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),\r
+ kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),\r
+ kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),\r
+ kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),\r
+ kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),\r
+ kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),\r
\r
kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),\r
- kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),\r
- kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),\r
- kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),\r
- kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),\r
- kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),\r
- kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),\r
+ kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),\r
+ kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),\r
+ kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),\r
+ kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),\r
+ kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),\r
+ kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),\r
\r
kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),\r
- kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),\r
- kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),\r
- kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),\r
- kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),\r
- kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),\r
- kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),\r
+ kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),\r
+ kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),\r
+ kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),\r
+ kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),\r
+ kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),\r
+ kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),\r
\r
kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),\r
- kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),\r
- kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),\r
- kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),\r
- kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),\r
- kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),\r
- kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),\r
+ kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),\r
+ kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),\r
+ kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),\r
+ kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),\r
+ kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),\r
+ kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),\r
\r
kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),\r
- kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),\r
- kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),\r
- kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),\r
- kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),\r
- kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),\r
- kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),\r
- kNONE_to_NONE = (int)0x80000000U,\r
+ kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),\r
+ kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),\r
+ kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),\r
+ kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),\r
+ kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),\r
+ kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),\r
+ kNONE_to_NONE = (int)0x80000000U,\r
} clock_attach_id_t;\r
\r
/* Clock dividers */\r
kCLOCK_DivSystickClk0 = 0,\r
kCLOCK_DivSystickClk1 = 1,\r
kCLOCK_DivArmTrClkDiv = 2,\r
- kCLOCK_DivFlexFrg0 = 8,\r
- kCLOCK_DivFlexFrg1 = 9,\r
- kCLOCK_DivFlexFrg2 = 10,\r
- kCLOCK_DivFlexFrg3 = 11,\r
- kCLOCK_DivFlexFrg4 = 12,\r
- kCLOCK_DivFlexFrg5 = 13,\r
- kCLOCK_DivFlexFrg6 = 14,\r
- kCLOCK_DivFlexFrg7 = 15,\r
- kCLOCK_DivAhbClk = 32,\r
- kCLOCK_DivClkOut = 33,\r
- kCLOCK_DivFrohfClk = 34,\r
- kCLOCK_DivWdtClk = 35,\r
+ kCLOCK_DivFlexFrg0 = 8,\r
+ kCLOCK_DivFlexFrg1 = 9,\r
+ kCLOCK_DivFlexFrg2 = 10,\r
+ kCLOCK_DivFlexFrg3 = 11,\r
+ kCLOCK_DivFlexFrg4 = 12,\r
+ kCLOCK_DivFlexFrg5 = 13,\r
+ kCLOCK_DivFlexFrg6 = 14,\r
+ kCLOCK_DivFlexFrg7 = 15,\r
+ kCLOCK_DivAhbClk = 32,\r
+ kCLOCK_DivClkOut = 33,\r
+ kCLOCK_DivFrohfClk = 34,\r
+ kCLOCK_DivWdtClk = 35,\r
kCLOCK_DivAdcAsyncClk = 37,\r
- kCLOCK_DivUsb0Clk = 38,\r
- kCLOCK_DivMClk = 43,\r
- kCLOCK_DivSctClk = 45,\r
- kCLOCK_DivSdioClk = 47,\r
- kCLOCK_DivPll0Clk = 49\r
+ kCLOCK_DivUsb0Clk = 38,\r
+ kCLOCK_DivMClk = 43,\r
+ kCLOCK_DivSctClk = 45,\r
+ kCLOCK_DivSdioClk = 47,\r
+ kCLOCK_DivPll0Clk = 49\r
} clock_div_name_t;\r
\r
/*******************************************************************************\r
*/\r
static inline void CLOCK_EnableClock(clock_ip_name_t clk)\r
{\r
- uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
- SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
}\r
/**\r
* @brief Disable the clock for specific IP.\r
*/\r
static inline void CLOCK_DisableClock(clock_ip_name_t clk)\r
{\r
- uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
- SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
}\r
/**\r
* @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).\r
* @return returns success or fail status.\r
*/\r
status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);\r
+/**\r
+ * @brief Initialize the PLU CLKIN clock to given frequency.\r
+ * @param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * @return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq);\r
/**\r
* @brief Configure the clock selection muxes.\r
* @param connection : Clock to be configured.\r
* @return Frequency of I2S MCLK Clock\r
*/\r
uint32_t CLOCK_GetI2SMClkFreq(void);\r
+/*! @brief Return Frequency of PLU CLKIN Clock\r
+ * @return Frequency of PLU CLKIN Clock\r
+ */\r
+uint32_t CLOCK_GetPLUClkInFreq(void);\r
+/*! @brief Return Frequency of FlexComm Clock\r
+ * @return Frequency of FlexComm Clock\r
+ */\r
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);\r
+/*! @brief Return Frequency of High speed SPI Clock\r
+ * @return Frequency of High speed SPI Clock\r
+ */\r
+uint32_t CLOCK_GetHsLspiClkFreq(void);\r
/*! @brief Return Frequency of CTimer functional Clock\r
* @return Frequency of CTimer functional Clock\r
*/\r
uint32_t CLOCK_GetSystickClkFreq(uint32_t id);\r
\r
/*! @brief Return PLL0 input clock rate\r
-* @return PLL0 input clock rate\r
-*/\r
+ * @return PLL0 input clock rate\r
+ */\r
uint32_t CLOCK_GetPLL0InClockRate(void);\r
\r
/*! @brief Return PLL1 input clock rate\r
-* @return PLL1 input clock rate\r
-*/\r
+ * @return PLL1 input clock rate\r
+ */\r
uint32_t CLOCK_GetPLL1InClockRate(void);\r
\r
/*! @brief Return PLL0 output clock rate\r
-* @param recompute : Forces a PLL rate recomputation if true\r
-* @return PLL0 output clock rate\r
-* @note The PLL rate is cached in the driver in a variable as\r
-* the rate computation function can take some time to perform. It\r
-* is recommended to use 'false' with the 'recompute' parameter.\r
-*/\r
+ * @param recompute : Forces a PLL rate recomputation if true\r
+ * @return PLL0 output clock rate\r
+ * @note The PLL rate is cached in the driver in a variable as\r
+ * the rate computation function can take some time to perform. It\r
+ * is recommended to use 'false' with the 'recompute' parameter.\r
+ */\r
uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);\r
\r
-/*! @brief Return PLL1 output clock rate\r
-* @param recompute : Forces a PLL rate recomputation if true\r
-* @return PLL1 output clock rate\r
-* @note The PLL rate is cached in the driver in a variable as\r
-* the rate computation function can take some time to perform. It\r
-* is recommended to use 'false' with the 'recompute' parameter.\r
-*/\r
-uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);\r
-\r
/*! @brief Enables and disables PLL0 bypass mode\r
-* @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass\r
-* @return PLL0 output clock rate\r
-*/\r
+ * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass\r
+ * @return PLL0 output clock rate\r
+ */\r
__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)\r
{\r
if (bypass)\r
}\r
\r
/*! @brief Enables and disables PLL1 bypass mode\r
-* @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass\r
-* @return PLL1 output clock rate\r
-*/\r
+ * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass\r
+ * @return PLL1 output clock rate\r
+ */\r
__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)\r
{\r
if (bypass)\r
}\r
\r
/*! @brief Check if PLL is locked or not\r
-* @return true if the PLL is locked, false if not locked\r
-*/\r
+ * @return true if the PLL is locked, false if not locked\r
+ */\r
__STATIC_INLINE bool CLOCK_IsPLL0Locked(void)\r
{\r
- return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0);\r
+ return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL);\r
}\r
\r
/*! @brief Check if PLL1 is locked or not\r
*/\r
__STATIC_INLINE bool CLOCK_IsPLL1Locked(void)\r
{\r
- return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0);\r
+ return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL);\r
}\r
\r
/*! @brief Store the current PLL0 rate\r
-* @param rate: Current rate of the PLL0\r
-* @return Nothing\r
-**/\r
+ * @param rate: Current rate of the PLL0\r
+ * @return Nothing\r
+ **/\r
void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);\r
\r
/*! @brief PLL configuration structure flags for 'flags' field\r
-* These flags control how the PLL configuration function sets up the PLL setup structure.<br>\r
-*\r
-* When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the\r
-* configuration structure must be assigned with the expected PLL frequency. If the\r
-* PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration\r
-* function and the driver will determine the PLL rate from the currently selected\r
-* PLL source. This flag might be used to configure the PLL input clock more accurately\r
-* when using the WDT oscillator or a more dyanmic CLKIN source.<br>\r
-*\r
-* When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the\r
-* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider\r
-* are not used.<br>\r
-*/\r
-#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */\r
-#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2)\r
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the\r
+ * configuration structure must be assigned with the expected PLL frequency. If the\r
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration\r
+ * function and the driver will determine the PLL rate from the currently selected\r
+ * PLL source. This flag might be used to configure the PLL input clock more accurately\r
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>\r
+ *\r
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the\r
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider\r
+ * are not used.<br>\r
+ */\r
+#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */\r
+#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U)\r
/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */\r
\r
/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency\r
kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */\r
kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */\r
kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */\r
- kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */\r
- kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */\r
- kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */\r
- kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */\r
+ kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */\r
+ kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */\r
+ kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */\r
+ kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */\r
} ss_progmodfm_t;\r
\r
/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth\r
*/\r
typedef enum _ss_progmoddp\r
{\r
- kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */\r
- kSS_MR_K1 = (1 << 23), /*!< k = 1 */\r
+ kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */\r
+ kSS_MR_K1 = (1 << 23), /*!< k = 1 */\r
kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */\r
- kSS_MR_K2 = (3 << 23), /*!< k = 2 */\r
- kSS_MR_K3 = (4 << 23), /*!< k = 3 */\r
- kSS_MR_K4 = (5 << 23), /*!< k = 4 */\r
- kSS_MR_K6 = (6 << 23), /*!< k = 6 */\r
- kSS_MR_K8 = (7 << 23) /*!< k = 8 */\r
+ kSS_MR_K2 = (3 << 23), /*!< k = 2 */\r
+ kSS_MR_K3 = (4 << 23), /*!< k = 3 */\r
+ kSS_MR_K4 = (5 << 23), /*!< k = 4 */\r
+ kSS_MR_K6 = (6 << 23), /*!< k = 6 */\r
+ kSS_MR_K8 = (7 << 23) /*!< k = 8 */\r
} ss_progmoddp_t;\r
\r
/*! @brief PLL Spread Spectrum (SS) Modulation waveform control\r
*/\r
typedef enum _ss_modwvctrl\r
{\r
- kSS_MC_NOC = (0 << 26), /*!< no compensation */\r
+ kSS_MC_NOC = (0 << 26), /*!< no compensation */\r
kSS_MC_RECC = (2 << 26), /*!< recommended setting */\r
kSS_MC_MAXC = (3 << 26), /*!< max. compensation */\r
} ss_modwvctrl_t;\r
\r
/*! @brief PLL configuration structure\r
-*\r
-* This structure can be used to configure the settings for a PLL\r
-* setup structure. Fill in the desired configuration for the PLL\r
-* and call the PLL setup function to fill in a PLL setup structure.\r
-*/\r
+ *\r
+ * This structure can be used to configure the settings for a PLL\r
+ * setup structure. Fill in the desired configuration for the PLL\r
+ * and call the PLL setup function to fill in a PLL setup structure.\r
+ */\r
typedef struct _pll_config\r
{\r
uint32_t desiredRate; /*!< Desired PLL rate in Hz */\r
} pll_config_t;\r
\r
/*! @brief PLL setup structure flags for 'flags' field\r
-* These flags control how the PLL setup function sets up the PLL\r
-*/\r
-#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */\r
-#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */\r
-#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */\r
-#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */\r
+ * These flags control how the PLL setup function sets up the PLL\r
+ */\r
+#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */\r
+#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */\r
+#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */\r
+#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */\r
\r
/*! @brief PLL0 setup structure\r
-* This structure can be used to pre-build a PLL setup configuration\r
-* at run-time and quickly set the PLL to the configuration. It can be\r
-* populated with the PLL setup function. If powering up or waiting\r
-* for PLL lock, the PLL input clock source should be configured prior\r
-* to PLL setup.\r
-*/\r
+ * This structure can be used to pre-build a PLL setup configuration\r
+ * at run-time and quickly set the PLL to the configuration. It can be\r
+ * populated with the PLL setup function. If powering up or waiting\r
+ * for PLL lock, the PLL input clock source should be configured prior\r
+ * to PLL setup.\r
+ */\r
typedef struct _pll_setup\r
{\r
uint32_t pllctrl; /*!< PLL control register PLL0CTRL */\r
} pll_setup_t;\r
\r
/*! @brief PLL status definitions\r
-*/\r
+ */\r
typedef enum _pll_error\r
{\r
- kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */\r
- kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */\r
- kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */\r
- kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */\r
- kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */\r
+ kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */\r
+ kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */\r
+ kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */\r
+ kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */\r
+ kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */\r
kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */\r
- kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */\r
- kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */\r
+ kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */\r
+ kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */\r
} pll_error_t;\r
\r
/*! @brief USB FS clock source definition. */\r
typedef enum _clock_usbfs_src\r
{\r
- kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */\r
- kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */\r
+ kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */\r
+ kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */\r
kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */\r
- kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */\r
+ kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */\r
\r
kCLOCK_UsbfsSrcNone =\r
SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */\r
} clock_usb_phy_src_t;\r
\r
/*! @brief Return PLL0 output clock rate from setup structure\r
-* @param pSetup : Pointer to a PLL setup structure\r
-* @return System PLL output clock rate the setup structure will generate\r
-*/\r
+ * @param pSetup : Pointer to a PLL setup structure\r
+ * @return System PLL output clock rate the setup structure will generate\r
+ */\r
uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);\r
\r
/*! @brief Set PLL0 output based on the passed PLL setup data\r
-* @param pControl : Pointer to populated PLL control structure to generate setup with\r
-* @param pSetup : Pointer to PLL setup structure to be filled\r
-* @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
-* @note Actual frequency for setup may vary from the desired frequency based on the\r
-* accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
-*/\r
+ * @param pControl : Pointer to populated PLL control structure to generate setup with\r
+ * @param pSetup : Pointer to PLL setup structure to be filled\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note Actual frequency for setup may vary from the desired frequency based on the\r
+ * accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+ */\r
pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);\r
\r
/*! @brief Set PLL output from PLL setup structure (precise frequency)\r
-* @param pSetup : Pointer to populated PLL setup structure\r
-* @param flagcfg : Flag configuration for PLL config structure\r
-* @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
-* @note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @param flagcfg : Flag configuration for PLL config structure\r
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);\r
\r
/**\r
-* @brief Set PLL output from PLL setup structure (precise frequency)\r
-* @param pSetup : Pointer to populated PLL setup structure\r
-* @return kStatus_PLL_Success on success, or PLL setup error code\r
-* @note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);\r
\r
/**\r
-* @brief Set PLL output from PLL setup structure (precise frequency)\r
-* @param pSetup : Pointer to populated PLL setup structure\r
-* @return kStatus_PLL_Success on success, or PLL setup error code\r
-* @note This function will power off the PLL, setup the PLL with the\r
-* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
-* and adjust system voltages to the new PLL rate. The function will not\r
-* alter any source clocks (ie, main systen clock) that may use the PLL,\r
-* so these should be setup prior to and after exiting the function.\r
-*/\r
+ * @brief Set PLL output from PLL setup structure (precise frequency)\r
+ * @param pSetup : Pointer to populated PLL setup structure\r
+ * @return kStatus_PLL_Success on success, or PLL setup error code\r
+ * @note This function will power off the PLL, setup the PLL with the\r
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+ * and adjust system voltages to the new PLL rate. The function will not\r
+ * alter any source clocks (ie, main systen clock) that may use the PLL,\r
+ * so these should be setup prior to and after exiting the function.\r
+ */\r
pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);\r
\r
/*! @brief Set PLL0 output based on the multiplier and input frequency\r
-* @param multiply_by : multiplier\r
-* @param input_freq : Clock input frequency of the PLL\r
-* @return Nothing\r
-* @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
-* function does not disable or enable PLL power, wait for PLL lock,\r
-* or adjust system voltages. These must be done in the application.\r
-* The function will not alter any source clocks (ie, main systen clock)\r
-* that may use the PLL, so these should be setup prior to and after\r
-* exiting the function.\r
-*/\r
+ * @param multiply_by : multiplier\r
+ * @param input_freq : Clock input frequency of the PLL\r
+ * @return Nothing\r
+ * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+ * function does not disable or enable PLL power, wait for PLL lock,\r
+ * or adjust system voltages. These must be done in the application.\r
+ * The function will not alter any source clocks (ie, main systen clock)\r
+ * that may use the PLL, so these should be setup prior to and after\r
+ * exiting the function.\r
+ */\r
void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);\r
\r
/*! @brief Disable USB clock.\r
-*\r
-* Disable USB clock.\r
-*/\r
+ *\r
+ * Disable USB clock.\r
+ */\r
static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)\r
{\r
CLOCK_DisableClock(clk);\r
}\r
\r
/*! @brief Enable USB Device FS clock.\r
-* @param src : clock source\r
-* @param freq: clock frequency\r
-* Enable USB Device Full Speed clock.\r
-*/\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB Device Full Speed clock.\r
+ */\r
bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);\r
\r
/*! @brief Enable USB HOST FS clock.\r
-* @param src : clock source\r
-* @param freq: clock frequency\r
-* Enable USB HOST Full Speed clock.\r
-*/\r
+ * @param src : clock source\r
+ * @param freq: clock frequency\r
+ * Enable USB HOST Full Speed clock.\r
+ */\r
bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);\r
\r
/*! @brief Enable USB phy clock.\r
-* Enable USB phy clock.\r
-*/\r
+ * Enable USB phy clock.\r
+ */\r
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);\r
\r
/*! @brief Enable USB Device HS clock.\r
-* Enable USB Device High Speed clock.\r
-*/\r
+ * Enable USB Device High Speed clock.\r
+ */\r
bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);\r
\r
/*! @brief Enable USB HOST HS clock.\r
-* Enable USB HOST High Speed clock.\r
-*/\r
+ * Enable USB HOST High Speed clock.\r
+ */\r
bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);\r
\r
#if defined(__cplusplus)\r
projects / freertos / blobdiff