commit 9f316c246baafa15c542a5aea81a94f26e3d6507

[freertos] / FreeRTOS / Demo / CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso / NXP_Code / drivers / fsl_common.c

diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
index 6bf905f9a3067639ca5f6560f2c56f3885a57149..f6284379c9a0ed2c3cacae987b165e3e8e659c4c 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.c
@@ -1,11 +1,10 @@
 /*\r
-* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
- * Copyright 2016-2018 NXP\r
-* All rights reserved.\r
-*\r
-*\r
-* SPDX-License-Identifier: BSD-3-Clause\r
-*/\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2019 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
 \r
 #include "fsl_common.h"\r
 #define SDK_MEM_MAGIC_NUMBER 12345U\r
@@ -118,30 +117,109 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
 {\r
     mem_align_cb_t *p_cb = NULL;\r
     uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);\r
-    void *p_align_addr, *p_addr = malloc(alignedsize);\r
+    union\r
+    {\r
+        void *pointer_value;\r
+        uint32_t unsigned_value;\r
+    } p_align_addr, p_addr;\r
+\r
+    p_addr.pointer_value = malloc(alignedsize);\r
 \r
-    if (!p_addr)\r
+    if (p_addr.pointer_value == NULL)\r
     {\r
         return NULL;\r
     }\r
 \r
-    p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);\r
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);\r
 \r
-    p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);\r
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);\r
     p_cb->identifier = SDK_MEM_MAGIC_NUMBER;\r
-    p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;\r
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);\r
 \r
-    return (void *)p_align_addr;\r
+    return p_align_addr.pointer_value;\r
 }\r
 \r
 void SDK_Free(void *ptr)\r
 {\r
-    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);\r
+    union\r
+    {\r
+        void *pointer_value;\r
+        uint32_t unsigned_value;\r
+    } p_free;\r
+    p_free.pointer_value = ptr;\r
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);\r
 \r
     if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)\r
     {\r
         return;\r
     }\r
 \r
-    free((void *)((uint32_t)ptr - p_cb->offset));\r
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;\r
+\r
+    free(p_free.pointer_value);\r
 }\r
+\r
+/*!\r
+ * @brief Delay function bases on while loop, every loop includes three instructions.\r
+ *\r
+ * @param count  Counts of loop needed for dalay.\r
+ */\r
+#ifndef __XCC__\r
+#if defined(__CC_ARM) /* This macro is arm v5 specific */\r
+/* clang-format off */\r
+__ASM static void DelayLoop(uint32_t count)\r
+{\r
+loop\r
+    SUBS R0, R0, #1\r
+    CMP  R0, #0\r
+    BNE  loop\r
+    BX   LR\r
+}\r
+/* clang-format on */\r
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)\r
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,\r
+ * use SUB and CMP here for compatibility */\r
+static void DelayLoop(uint32_t count)\r
+{\r
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));\r
+    __ASM volatile(\r
+        "loop:                          \n"\r
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)\r
+        "    SUB    R0, R0, #1          \n"\r
+#else\r
+        "    SUBS   R0, R0, #1          \n"\r
+#endif\r
+        "    CMP    R0, #0              \n"\r
+\r
+        "    BNE    loop                \n");\r
+}\r
+#endif /* defined(__CC_ARM) */\r
+\r
+/*!\r
+ * @brief Delay at least for some time.\r
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,\r
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.\r
+ *\r
+ * @param delay_us  Delay time in unit of microsecond.\r
+ * @param coreClock_Hz  Core clock frequency with Hz.\r
+ */\r
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)\r
+{\r
+    assert(0U != delay_us);\r
+    uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);\r
+    assert(count <= UINT32_MAX);\r
+\r
+    /* Divide value may be different in various environment to ensure delay is precise.\r
+     * Every loop count includes three instructions, due to Cortex-M7 sometimes executes\r
+     * two instructions in one period, through test here set divide 2. Other M cores use\r
+     * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does\r
+     * not matter because other instructions outside while loop is enough to fill the time.\r
+     */\r
+#if (__CORTEX_M == 7)\r
+    count = count / 2U;\r
+#else\r
+    count = count / 4U;\r
+#endif\r
+    DelayLoop((uint32_t)count);\r
+}\r
+#endif\r