/*\r
* Copyright (c) 2016, Freescale Semiconductor, Inc.\r
- * Copyright 2016-2017 NXP\r
+ * Copyright 2016-2019 NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
\r
/*! @name Driver version */\r
/*@{*/\r
-/*! @brief IOCON driver version 2.0.0. */\r
-#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*! @brief IOCON driver version 2.1.1. */\r
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))\r
/*@}*/\r
\r
/**\r
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
#define IOCON_S_MODE_1CLK \\r
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE_2CLK \\r
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE_3CLK \\r
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
#endif\r
\r
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
#define IOCON_S_MODE_1CLK \\r
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE_2CLK \\r
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE_3CLK \\r
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
- */\r
+ */\r
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
#endif\r
\r