/*\r
- * Copyright (c) 2017, NXP\r
+ * Copyright 2017, NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))\r
/*@}*/\r
\r
-\r
-/** @brief Low Power main structure */\r
-typedef enum\r
+/* Power mode configuration API parameter */\r
+typedef enum _power_mode_config\r
{\r
- VD_AON = 0x0, /*!< Digital Always On power domain */\r
- VD_MEM = 0x1, /*!< Memories (SRAM) power domain */\r
- VD_DCDC = 0x2, /*!< Core logic power domain */\r
- VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */\r
-} LPC_POWER_DOMAIN_T;\r
-\r
-/** @brief Low Power main structure */\r
-typedef struct\r
-{ /* */\r
- __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */\r
- __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules\r
- in the different Low power modes, including ROM */\r
- __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances\r
- in the different Low power modes */\r
- __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */\r
- __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */\r
- __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */\r
- __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */\r
- __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes\r
- in case an interrupt is pending when the processor request deepsleep */\r
- __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */\r
- __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */\r
- __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/\r
- __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some\r
- interrupt handlers)*/\r
-} LPC_LOWPOWER_T;\r
-\r
-/* */\r
-#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */\r
-\r
-/* Low Power modes */\r
-#define LOWPOWER_CFG_LPMODE_INDEX 0\r
-#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX)\r
-#define LOWPOWER_CFG_SELCLOCK_INDEX 2\r
-#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX)\r
-#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3\r
-#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX)\r
-#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4\r
-#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX)\r
-#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5\r
-#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX)\r
-\r
-#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */\r
-#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */\r
-#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */\r
-#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */\r
-#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */\r
-\r
-#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */\r
-#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/\r
-\r
-#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */\r
-#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */\r
-\r
-#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */\r
-#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */\r
-\r
-#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */\r
-#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */\r
-\r
-/* CPU Retention Control*/\r
-#define LOWPOWER_CPURETCTRL_ENA_INDEX 0\r
-#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX)\r
-#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1\r
-#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX)\r
-#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14\r
-#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX)\r
-\r
-#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */\r
-#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */\r
+ kPmu_Sleep = 0U,\r
+ kPmu_Deep_Sleep = 1U,\r
+ kPmu_PowerDown = 2U,\r
+ kPmu_Deep_PowerDown = 3U,\r
+} power_mode_cfg_t;\r
\r
/**\r
* @brief Analog components power modes control during low power modes\r
*/\r
typedef enum pd_bits\r
{\r
- kPDRUNCFG_PD_DCDC = (1UL << 0),\r
- kPDRUNCFG_PD_BIAS = (1UL << 1),\r
- kPDRUNCFG_PD_BODCORE = (1UL << 2),\r
- kPDRUNCFG_PD_BODVBAT = (1UL << 3),\r
- kPDRUNCFG_PD_FRO1M = (1UL << 4),\r
- kPDRUNCFG_PD_FRO192M = (1UL << 5),\r
- kPDRUNCFG_PD_FRO32K = (1UL << 6),\r
- kPDRUNCFG_PD_XTAL32K = (1UL << 7),\r
- kPDRUNCFG_PD_XTAL32M = (1UL << 8),\r
- kPDRUNCFG_PD_PLL0 = (1UL << 9),\r
- kPDRUNCFG_PD_PLL1 = (1UL << 10),\r
- kPDRUNCFG_PD_USB0_PHY = (1UL << 11),\r
- kPDRUNCFG_PD_USB1_PHY = (1UL << 12),\r
- kPDRUNCFG_PD_COMP = (1UL << 13),\r
- kPDRUNCFG_PD_TEMPSENS = (1UL << 14),\r
- kPDRUNCFG_PD_GPADC = (1UL << 15),\r
- kPDRUNCFG_PD_LDOMEM = (1UL << 16),\r
+ kPDRUNCFG_PD_DCDC = (1UL << 0),\r
+ kPDRUNCFG_PD_BIAS = (1UL << 1),\r
+ kPDRUNCFG_PD_BODCORE = (1UL << 2),\r
+ kPDRUNCFG_PD_BODVBAT = (1UL << 3),\r
+ kPDRUNCFG_PD_FRO1M = (1UL << 4),\r
+ kPDRUNCFG_PD_FRO192M = (1UL << 5),\r
+ kPDRUNCFG_PD_FRO32K = (1UL << 6),\r
+ kPDRUNCFG_PD_XTAL32K = (1UL << 7),\r
+ kPDRUNCFG_PD_XTAL32M = (1UL << 8),\r
+ kPDRUNCFG_PD_PLL0 = (1UL << 9),\r
+ kPDRUNCFG_PD_PLL1 = (1UL << 10),\r
+ kPDRUNCFG_PD_USB0_PHY = (1UL << 11),\r
+ kPDRUNCFG_PD_USB1_PHY = (1UL << 12),\r
+ kPDRUNCFG_PD_COMP = (1UL << 13),\r
+ kPDRUNCFG_PD_TEMPSENS = (1UL << 14),\r
+ kPDRUNCFG_PD_GPADC = (1UL << 15),\r
+ kPDRUNCFG_PD_LDOMEM = (1UL << 16),\r
kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),\r
- kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),\r
- kPDRUNCFG_PD_LDOGPADC = (1UL << 19),\r
- kPDRUNCFG_PD_LDOXO32M = (1UL << 20),\r
- kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),\r
- kPDRUNCFG_PD_RNG = (1UL << 22),\r
- kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),\r
- kPDRUNCFG_PD_ROM = (1UL << 24),\r
-\r
+ kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),\r
+ kPDRUNCFG_PD_LDOGPADC = (1UL << 19),\r
+ kPDRUNCFG_PD_LDOXO32M = (1UL << 20),\r
+ kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),\r
+ kPDRUNCFG_PD_RNG = (1UL << 22),\r
+ kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),\r
+ kPDRUNCFG_PD_ROM = (1UL << 24),\r
/*\r
This enum member has no practical meaning,it is used to avoid MISRA issue,\r
user should not trying to use it.\r
kPDRUNCFG_ForceUnsigned = 0x80000000U,\r
} pd_bit_t;\r
\r
-/**\r
- * @brief SRAM instances retention control during low power modes\r
- */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */\r
-#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */\r
-\r
-/**\r
- * @brief SRAM Low Power Modes\r
- */\r
-\r
-#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL)\r
-#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */\r
-#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */\r
-#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */\r
-#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */\r
-#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */\r
-\r
/*@brief BOD VBAT level */\r
typedef enum _power_bod_vbat_level\r
{\r
kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */\r
} power_bod_vbat_level_t;\r
\r
+/*@brief BOD Hysteresis control */\r
+typedef enum _power_bod_hyst\r
+{\r
+ kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */\r
+ kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */\r
+ kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */\r
+ kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */\r
+} power_bod_hyst_t;\r
+\r
/*@brief BOD core level */\r
typedef enum _power_bod_core_level\r
{\r
kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */\r
} power_bod_core_level_t;\r
\r
-/*@brief BOD Hysteresis control */\r
-typedef enum _power_bod_hyst\r
-{\r
- kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */\r
- kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */\r
- kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */\r
- kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */\r
-} power_bod_hyst_t;\r
-\r
/**\r
- * @brief LDO Voltage control in Low Power Modes\r
- */\r
-#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0\r
-#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX)\r
-#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5\r
-#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX)\r
-#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10\r
-#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX)\r
-#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19\r
-#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX)\r
-#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24\r
-#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)\r
-#define LOWPOWER_VOLTAGE_DCDC_INDEX 29\r
-#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX)\r
-\r
-/**\r
- * @brief Always On and Memories LDO voltage settings\r
- */\r
-\r
-typedef enum _v_ao\r
-{\r
- // V_AO_1P220 1.22 = 0, /*!< 1.22 V */\r
- V_AO_0P700 = 1, /*!< 0.7 V */\r
- V_AO_0P725 = 2, /*!< 0.725 V */\r
- V_AO_0P750 = 3, /*!< 0.75 V */\r
- V_AO_0P775 = 4, /*!< 0.775 V */\r
- V_AO_0P800 = 5, /*!< 0.8 V */\r
- V_AO_0P825 = 6, /*!< 0.825 V */\r
- V_AO_0P850 = 7, /*!< 0.85 V */\r
- V_AO_0P875 = 8, /*!< 0.875 V */\r
- V_AO_0P900 = 9, /*!< 0.9 V */\r
- V_AO_0P960 = 10, /*!< 0.96 V */\r
- V_AO_0P970 = 11, /*!< 0.97 V */\r
- V_AO_0P980 = 12, /*!< 0.98 V */\r
- V_AO_0P990 = 13, /*!< 0.99 V */\r
- V_AO_1P000 = 14, /*!< 1 V */\r
- V_AO_1P010 = 15, /*!< 1.01 V */\r
- V_AO_1P020 = 16, /*!< 1.02 V */\r
- V_AO_1P030 = 17, /*!< 1.03 V */\r
- V_AO_1P040 = 18, /*!< 1.04 V */\r
- V_AO_1P050 = 19, /*!< 1.05 V */\r
- V_AO_1P060 = 20, /*!< 1.06 V */\r
- V_AO_1P070 = 21, /*!< 1.07 V */\r
- V_AO_1P080 = 22, /*!< 1.08 V */\r
- V_AO_1P090 = 23, /*!< 1.09 V */\r
- V_AO_1P100 = 24, /*!< 1.1 V */\r
- V_AO_1P110 = 25, /*!< 1.11 V */\r
- V_AO_1P120 = 26, /*!< 1.12 V */\r
- V_AO_1P130 = 27, /*!< 1.13 V */\r
- V_AO_1P140 = 28, /*!< 1.14 V */\r
- V_AO_1P150 = 29, /*!< 1.15 V */\r
- V_AO_1P160 = 30, /*!< 1.16 V */\r
- V_AO_1P220 = 31 /*!< 1.22 V */\r
-} v_ao_t;\r
-\r
-/**\r
- * @brief Deep Sleep LDO voltage settings\r
- */\r
-typedef enum _v_deepsleep\r
-{\r
- V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */\r
- V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */\r
- V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */\r
- V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */\r
- V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */\r
- V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */\r
- V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */\r
- V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */\r
-} v_deepsleep_t;\r
-\r
-/**\r
- * @brief DCDC voltage settings\r
- */\r
-typedef enum _v_dcdc\r
-{\r
- V_DCDC_0P950 = 0, /*!< 0.95 V */\r
- V_DCDC_0P975 = 1, /*!< 0.975 V */\r
- V_DCDC_1P000 = 2, /*!< 1 V */\r
- V_DCDC_1P025 = 3, /*!< 1.025 V */\r
- V_DCDC_1P050 = 4, /*!< 1.050 V */\r
- V_DCDC_1P075 = 5, /*!< 1.075 V */\r
- V_DCDC_1P100 = 6, /*!< 1.1 V */\r
- V_DCDC_1P125 = 7, /*!< 1.125 V */\r
- V_DCDC_1P150 = 8, /*!< 1.150 V */\r
- V_DCDC_1P175 = 9, /*!< 1.175 V */\r
- V_DCDC_1P200 = 10 /*!< 1.2 V */\r
-} v_dcdc_t;\r
-/**\r
- * @brief LDO_FLASH_NV & LDO_USB voltage settings\r
+ * @brief SRAM instances retention control during low power modes\r
*/\r
-typedef enum _v_flashnv\r
-{\r
- V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */\r
- V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */\r
- V_LDOFLASHNV_1P750 = 2, /*!< 1 V */\r
- V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */\r
- V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */\r
- V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */\r
- V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */\r
- V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */\r
-} v_flashnv_t;\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \\r
+ (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \\r
+ (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \\r
+ (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \\r
+ (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \\r
+ (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \\r
+ (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \\r
+ (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \\r
+ (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \\r
+ (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \\r
+ (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \\r
+ (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \\r
+ (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \\r
+ (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \\r
+ (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \\r
+ (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \\r
+ (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */\r
\r
/**\r
* @brief Low Power Modes Wake up sources\r
*/\r
-\r
-#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/\r
-#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
-#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
-#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */\r
-#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */\r
-#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */\r
-#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
-#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */\r
-// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/\r
+#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */\r
+#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */\r
+#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */\r
+#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */\r
+#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
// reserved (1ULL << 25)\r
// reserved (1ULL << 26)\r
-#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
-#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */\r
-#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
-#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
+#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
+#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */\r
+#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
// reserved (1ULL << 39)\r
// reserved (1ULL << 40)\r
// reserved (1ULL << 41)\r
-#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */\r
+#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */\r
// reserved (1ULL << 43)\r
// reserved (1ULL << 44)\r
// reserved (1ULL << 45)\r
// reserved (1ULL << 46)\r
-#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */\r
-#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_SEC_VIO (1ULL << 53)\r
-#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */\r
-#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */\r
-#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */\r
-#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */\r
-#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */\r
-#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */\r
+#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_VIO (1ULL << 53)\r
+#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */\r
+#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */\r
+#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */\r
+#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */\r
+#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */\r
// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60)\r
// reserved WAKEUP_PVTVF0_RED (1ULL << 61)\r
// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62)\r
-#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */\r
-\r
+#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */\r
\r
/**\r
* @brief Sleep Postpone\r
*/\r
-#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */\r
-#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */\r
-#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
-#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
-#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */\r
-\r
+#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */\r
+#define LOWPOWER_HWWAKE_PERIPHERALS \\r
+ (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \\r
+ peripheral clocking to wake up temporarily while the related status is asserted */\r
+#define LOWPOWER_HWWAKE_SDMA0 \\r
+ (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \\r
+ completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
+#define LOWPOWER_HWWAKE_SDMA1 \\r
+ (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \\r
+ completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
+#define LOWPOWER_HWWAKE_ENABLE_FRO192M \\r
+ (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \\r
+ LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */\r
+\r
+#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */\r
+#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */\r
/**\r
* @brief Wake up I/O sources\r
*/\r
-#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */\r
-#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */\r
-#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */\r
-#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */\r
-\r
-#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */\r
-#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */\r
-#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */\r
-#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */\r
-\r
-/**\r
- * @brief Wake up timers configuration in Low Power Modes\r
- */\r
-#define LOWPOWER_TIMERCFG_CTRL_INDEX 0\r
-#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX)\r
-#define LOWPOWER_TIMERCFG_TIMER_INDEX 1\r
-#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX)\r
-#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4\r
-#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX)\r
-\r
-#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */\r
-#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */\r
-\r
-/**\r
- * @brief Primary Wake up timers configuration in Low Power Modes\r
- */\r
-#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */\r
-#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */\r
-#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */\r
-\r
-#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */\r
-#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */\r
-\r
-//! @brief Interface for lowpower functions\r
-typedef struct LowpowerDriverInterface\r
-{\r
- void (*power_cycle_cpu_and_flash)(void);\r
- void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg);\r
-} lowpower_driver_interface_t;\r
-\r
-/* Power mode configuration API parameter */\r
-typedef enum _power_mode_config\r
-{\r
- kPmu_Sleep = 0U,\r
- kPmu_Deep_Sleep = 1U,\r
- kPmu_PowerDown = 2U,\r
- kPmu_Deep_PowerDown = 3U,\r
-} power_mode_cfg_t;\r
-\r
-/*******************************************************************************\r
- * API\r
- ******************************************************************************/\r
+#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */\r
+\r
+#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */\r
+#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */\r
+#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */\r
+#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */\r
+\r
+#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */\r
+#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */\r
+#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */\r
+#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */\r
+\r
+#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */\r
+#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */\r
+#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */\r
+#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */\r
+\r
+#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */\r
+#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */\r
+\r
+#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \\r
+ 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */\r
+#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \\r
+ 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */\r
+#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \\r
+ 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */\r
+#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \\r
+ 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */\r
+#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */\r
+#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */\r
+#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */\r
+#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \\r
+ (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */\r
\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
\r
/*!\r
* @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral\r
static inline void POWER_EnablePD(pd_bit_t en)\r
{\r
/* PDRUNCFGSET */\r
- PMC->PDRUNCFGSET0 = en;\r
+ PMC->PDRUNCFGSET0 = (uint32_t)en;\r
}\r
\r
/*!\r
static inline void POWER_DisablePD(pd_bit_t en)\r
{\r
/* PDRUNCFGCLR */\r
- PMC->PDRUNCFGCLR0 = en;\r
+ PMC->PDRUNCFGCLR0 = (uint32_t)en;\r
}\r
\r
/*!\r
static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)\r
{\r
PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) |\r
- PMC_BODVBAT_HYST(hyst);\r
+ PMC_BODVBAT_HYST(hyst);\r
PMC->RESETCTRL =\r
(PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset);\r
}\r
\r
+#if defined(PMC_BODCORE_TRIGLVL_MASK)\r
/*!\r
* @brief set BOD core level.\r
*\r
static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset)\r
{\r
PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) |\r
- PMC_BODCORE_HYST(hyst);\r
+ PMC_BODCORE_HYST(hyst);\r
PMC->RESETCTRL =\r
(PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset);\r
}\r
+#endif\r
\r
/*!\r
* @brief API to enable deep sleep bit in the ARM Core.\r
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;\r
}\r
\r
-/*!\r
- * @brief API to power down flash controller.\r
- *\r
- * @param none\r
- * @return none\r
- */\r
-static inline void POWER_PowerDownFlash(void)\r
-{\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
- CLOCK_DisableClock(kCLOCK_Flash);\r
-\r
- /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
- CLOCK_DisableClock(kCLOCK_Fmc);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-}\r
-\r
-/*!\r
- * @brief API to power up flash controller.\r
- *\r
- * @param none\r
- * @return none\r
- */\r
-static inline void POWER_PowerUpFlash(void)\r
-{\r
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
- /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
- CLOCK_EnableClock(kCLOCK_Fmc);\r
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
-}\r
-\r
-/**\r
- * @brief Configures and enters in low power mode\r
- * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters\r
- * @return Nothing\r
- *\r
- * !!! IMPORTANT NOTES :\r
- * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the\r
- * API.\r
- * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk\r
- * of Dead Lock).\r
- * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip\r
- * reset)\r
- */\r
-void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg);\r
-\r
/**\r
* @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event\r
* This MUST BE EXECUTED outside the Flash:\r
*\r
* !!! IMPORTANT NOTES :\r
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
- * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
- * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
- * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
- reset)\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in\r
+ case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be\r
+ restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip\r
+ reset) reset)\r
*/\r
-void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl);\r
+void POWER_EnterDeepSleep(uint32_t exclude_from_pd,\r
+ uint32_t sram_retention_ctrl,\r
+ uint64_t wakeup_interrupts,\r
+ uint32_t hardware_wake_ctrl);\r
\r
/**\r
* @brief Configures and enters in POWERDOWN low power mode\r
*\r
* !!! IMPORTANT NOTES :\r
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
- * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
- * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
- * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl")\r
- * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
- reset)\r
- */\r
-void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl);\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in\r
+ case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be\r
+ restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance\r
+ containing the stack used to call this function WILL BE preserved during low power (via parameter\r
+ "sram_retention_ctrl")\r
+ * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip\r
+ reset) reset)\r
+ */\r
+\r
+void POWER_EnterPowerDown(uint32_t exclude_from_pd,\r
+ uint32_t sram_retention_ctrl,\r
+ uint64_t wakeup_interrupts,\r
+ uint32_t cpu_retention_ctrl);\r
\r
/**\r
* @brief Configures and enters in DEEPPOWERDOWN low power mode\r
*\r
* !!! IMPORTANT NOTES :\r
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
- * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
- * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
- * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if\r
+ DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be\r
+ restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip\r
+ reset)\r
*/\r
-void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl);\r
+void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd,\r
+ uint32_t sram_retention_ctrl,\r
+ uint64_t wakeup_interrupts,\r
+ uint32_t wakeup_io_ctrl);\r
\r
/**\r
* @brief Configures and enters in SLEEP low power mode\r
/**\r
* @brief Sets board-specific trim values for 16MHz XTAL\r
* @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
- * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
- * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF\r
+ * becomes 120\r
+ * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF\r
+ * becomes 120\r
* @return none\r
* @note Following default Values can be used:\r
* pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600\r
* pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20\r
* pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40\r
*/\r
-extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100);\r
+extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100,\r
+ int32_t pi32_16MfXtalPPcbParCappF_x100,\r
+ int32_t pi32_16MfXtalNPcbParCappF_x100);\r
/**\r
* @brief Sets board-specific trim values for 32kHz XTAL\r
* @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
- * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
- * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF\r
+ becomes 120\r
+ * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF\r
+ becomes 120\r
\r
* @return none\r
* @note Following default Values can be used:\r
* pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40\r
* pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40\r
*/\r
-extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100);\r
+extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,\r
+ int32_t pi32_32kfXtalPPcbParCappF_x100,\r
+ int32_t pi32_32kfXtalNPcbParCappF_x100);\r
/**\r
* @brief Enables and sets LDO for 16MHz XTAL\r
* @param none\r
* @return none\r
*/\r
extern void POWER_SetXtal16mhzLdo(void);\r
+\r
/**\r
* @brief Set up 16-MHz XTAL Trimmings\r
* @param amp Amplitude\r
*/\r
extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);\r
#ifdef __cplusplus\r
- }\r
+}\r
#endif\r
\r
/**\r
projects / freertos / blobdiff