--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright (c) 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_RESET_H_\r
+#define _FSL_RESET_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include "fsl_device_registers.h"\r
+\r
+/*!\r
+ * @addtogroup ksdk_common\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief reset driver version 2.0.0. */\r
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Enumeration for peripheral reset control bits\r
+ *\r
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers\r
+ */\r
+typedef enum _SYSCON_RSTn\r
+{\r
+ kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */\r
+ kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */\r
+ kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */\r
+ kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */\r
+ kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */\r
+ kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */\r
+ kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */\r
+ kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */\r
+ kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */\r
+ kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */\r
+ kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */\r
+ kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */\r
+ kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */\r
+ kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */\r
+ kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */\r
+ kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */\r
+ kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */\r
+ kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */\r
+ kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */\r
+ kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */\r
+ kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */\r
+ kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */\r
+\r
+ kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */\r
+ kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */\r
+ kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */\r
+ kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */\r
+ kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */\r
+ kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */\r
+ kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */\r
+ kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */\r
+ kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */\r
+ kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */\r
+ kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */\r
+ kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */\r
+ kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */\r
+ kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */\r
+ kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */\r
+ kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */\r
+ kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */\r
+ kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */\r
+ kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */\r
+ kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */\r
+\r
+ kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */\r
+ kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */\r
+ kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */\r
+ kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */\r
+ kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */\r
+ kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */\r
+ kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */\r
+ kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */\r
+ kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */\r
+ kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */\r
+ kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */\r
+ kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */\r
+ kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */\r
+ kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */\r
+ kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */\r
+ kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */\r
+ kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */\r
+ kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */\r
+ kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */\r
+ kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */\r
+ kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */\r
+ kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */\r
+ kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */\r
+ kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */\r
+ kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */\r
+ kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */\r
+ kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */\r
+ kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */\r
+ kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */\r
+} SYSCON_RSTn_t;\r
+\r
+/** Array initializers with peripheral reset bits **/\r
+#define ADC_RSTS \\r
+ { \\r
+ kADC0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for ADC peripheral */\r
+#define AES_RSTS \\r
+ { \\r
+ kAES_RST_SHIFT_RSTn \\r
+ } /* Reset bits for AES peripheral */\r
+#define CRC_RSTS \\r
+ { \\r
+ kCRC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CRC peripheral */\r
+#define CTIMER_RSTS \\r
+ { \\r
+ kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \\r
+ kCTIMER4_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CTIMER peripheral */\r
+#define DMA_RSTS_N \\r
+ { \\r
+ kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \\r
+ } /* Reset bits for DMA peripheral */\r
+\r
+#define FLEXCOMM_RSTS \\r
+ { \\r
+ kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \\r
+ kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \\r
+ } /* Reset bits for FLEXCOMM peripheral */\r
+#define GINT_RSTS \\r
+ { \\r
+ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */\r
+#define GPIO_RSTS_N \\r
+ { \\r
+ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \\r
+ kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GPIO peripheral */\r
+#define INPUTMUX_RSTS \\r
+ { \\r
+ kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \\r
+ } /* Reset bits for INPUTMUX peripheral */\r
+#define IOCON_RSTS \\r
+ { \\r
+ kIOCON_RST_SHIFT_RSTn \\r
+ } /* Reset bits for IOCON peripheral */\r
+#define FLASH_RSTS \\r
+ { \\r
+ kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for Flash peripheral */\r
+#define MRT_RSTS \\r
+ { \\r
+ kMRT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for MRT peripheral */\r
+#define OTP_RSTS \\r
+ { \\r
+ kOTP_RST_SHIFT_RSTn \\r
+ } /* Reset bits for OTP peripheral */\r
+#define PINT_RSTS \\r
+ { \\r
+ kPINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for PINT peripheral */\r
+#define RNG_RSTS \\r
+ { \\r
+ kRNG_RST_SHIFT_RSTn \\r
+ } /* Reset bits for RNG peripheral */\r
+#define SDIO_RST \\r
+ { \\r
+ kSDIO_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SDIO peripheral */\r
+#define SCT_RSTS \\r
+ { \\r
+ kSCT0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SCT peripheral */\r
+#define SPIFI_RSTS \\r
+ { \\r
+ kSPIFI_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SPIFI peripheral */\r
+#define USB0D_RST \\r
+ { \\r
+ kUSB0D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0D peripheral */\r
+#define USB0HMR_RST \\r
+ { \\r
+ kUSB0HMR_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HMR peripheral */\r
+#define USB0HSL_RST \\r
+ { \\r
+ kUSB0HSL_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HSL peripheral */\r
+#define USB1H_RST \\r
+ { \\r
+ kUSB1H_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1H peripheral */\r
+#define USB1D_RST \\r
+ { \\r
+ kUSB1D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1D peripheral */\r
+#define USB1RAM_RST \\r
+ { \\r
+ kUSB1RAM_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1RAM peripheral */\r
+#define UTICK_RSTS \\r
+ { \\r
+ kUTICK_RST_SHIFT_RSTn \\r
+ } /* Reset bits for UTICK peripheral */\r
+#define WWDT_RSTS \\r
+ { \\r
+ kWWDT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for WWDT peripheral */\r
+#define CAPT_RSTS_N \\r
+ { \\r
+ kCAP0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CAPT peripheral */\r
+#define PLU_RSTS_N \\r
+ { \\r
+ kPLULUT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for PLU peripheral */\r
+#define OSTIMER_RSTS \\r
+ { \\r
+ kOSTIMER0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for OSTIMER peripheral */\r
+typedef SYSCON_RSTn_t reset_ip_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief Assert reset to peripheral.\r
+ *\r
+ * Asserts reset signal to specified peripheral module.\r
+ *\r
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Clear reset to peripheral.\r
+ *\r
+ * Clears reset signal to specified peripheral module, allows it to operate.\r
+ *\r
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Reset peripheral module.\r
+ *\r
+ * Reset peripheral module.\r
+ *\r
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_PeripheralReset(reset_ip_name_t peripheral);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_RESET_H_ */\r
projects / freertos / blobdiff