/*\r
* Copyright (c) 2016, Freescale Semiconductor, Inc.\r
- * Copyright 2016-2018 NXP\r
+ * Copyright 2016-2019 NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
#include "fsl_device_registers.h"\r
#include "fsl_flexcomm.h"\r
\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
/* Component ID definition, used by tools. */\r
#ifndef FSL_COMPONENT_ID\r
#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"\r
#endif\r
\r
-enum _usart_transfer_states\r
+/*!\r
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`\r
+ */\r
+typedef union usart_to_flexcomm\r
+{\r
+ flexcomm_usart_irq_handler_t usart_master_handler;\r
+ flexcomm_irq_handler_t flexcomm_handler;\r
+} usart_to_flexcomm_t;\r
+\r
+enum\r
{\r
kUSART_TxIdle, /* TX idle. */\r
kUSART_TxBusy, /* TX busy. */\r
/*! brief Returns instance number for USART peripheral base address. */\r
uint32_t USART_GetInstance(USART_Type *base)\r
{\r
- int i;\r
+ uint32_t i;\r
\r
- for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)\r
+ for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)\r
{\r
if ((uint32_t)base == s_usartBaseAddrs[i])\r
{\r
- return i;\r
+ break;\r
}\r
}\r
\r
- assert(false);\r
- return 0;\r
+ assert(i < FSL_FEATURE_SOC_USART_COUNT);\r
+ return i;\r
}\r
\r
/*!\r
\r
/* Check arguments */\r
assert(NULL != handle);\r
+ uint16_t rxRingBufferHead = handle->rxRingBufferHead;\r
+ uint16_t rxRingBufferTail = handle->rxRingBufferTail;\r
\r
- if (handle->rxRingBufferTail > handle->rxRingBufferHead)\r
+ if (rxRingBufferTail > rxRingBufferHead)\r
{\r
- size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);\r
+ size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;\r
}\r
else\r
{\r
- size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);\r
+ size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;\r
}\r
return size;\r
}\r
assert(NULL != ringBuffer);\r
\r
/* Setup the ringbuffer address */\r
- handle->rxRingBuffer = ringBuffer;\r
+ handle->rxRingBuffer = ringBuffer;\r
handle->rxRingBufferSize = ringBufferSize;\r
handle->rxRingBufferHead = 0U;\r
handle->rxRingBufferTail = 0U;\r
assert(NULL != base);\r
assert(NULL != handle);\r
\r
- if (handle->rxState == kUSART_RxIdle)\r
+ if (handle->rxState == (uint8_t)kUSART_RxIdle)\r
{\r
base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;\r
}\r
- handle->rxRingBuffer = NULL;\r
+ handle->rxRingBuffer = NULL;\r
handle->rxRingBufferSize = 0U;\r
handle->rxRingBufferHead = 0U;\r
handle->rxRingBufferTail = 0U;\r
int result;\r
\r
/* check arguments */\r
- assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));\r
- if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))\r
+ assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));\r
+ if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))\r
{\r
return kStatus_InvalidArgument;\r
}\r
return result;\r
}\r
\r
- /* setup baudrate */\r
- result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);\r
- if (kStatus_Success != result)\r
- {\r
- return result;\r
- }\r
-\r
if (config->enableTx)\r
{\r
/* empty and enable txFIFO */\r
}\r
/* setup configuration and enable USART */\r
base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |\r
- USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;\r
+ USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |\r
+ USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |\r
+ USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;\r
+\r
+ /* Setup baudrate */\r
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);\r
+ if (kStatus_Success != result)\r
+ {\r
+ return result;\r
+ }\r
+ /* Setting continuous Clock configuration. used for synchronous mode. */\r
+ USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);\r
+\r
return kStatus_Success;\r
}\r
\r
{\r
/* Check arguments */\r
assert(NULL != base);\r
- while (!(base->STAT & USART_STAT_TXIDLE_MASK))\r
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))\r
{\r
}\r
/* Disable interrupts, disable dma requests, disable peripheral */\r
assert(NULL != config);\r
\r
/* Initializes the configure structure to zero. */\r
- memset(config, 0, sizeof(*config));\r
+ (void)memset(config, 0, sizeof(*config));\r
\r
/* Set always all members ! */\r
- config->baudRate_Bps = 115200U;\r
- config->parityMode = kUSART_ParityDisabled;\r
- config->stopBitCount = kUSART_OneStopBit;\r
- config->bitCountPerChar = kUSART_8BitsPerChar;\r
- config->loopback = false;\r
- config->enableRx = false;\r
- config->enableTx = false;\r
- config->txWatermark = kUSART_TxFifo0;\r
- config->rxWatermark = kUSART_RxFifo1;\r
+ config->baudRate_Bps = 115200U;\r
+ config->parityMode = kUSART_ParityDisabled;\r
+ config->stopBitCount = kUSART_OneStopBit;\r
+ config->bitCountPerChar = kUSART_8BitsPerChar;\r
+ config->loopback = false;\r
+ config->enableRx = false;\r
+ config->enableTx = false;\r
+ config->txWatermark = kUSART_TxFifo0;\r
+ config->rxWatermark = kUSART_RxFifo1;\r
+ config->syncMode = kUSART_SyncModeDisabled;\r
+ config->enableContinuousSCLK = false;\r
+ config->clockPolarity = kUSART_RxSampleOnFallingEdge;\r
}\r
\r
/*!\r
*\r
* param base USART peripheral base address.\r
* param baudrate_Bps USART baudrate to be set.\r
- * param srcClock_Hz USART clock source freqency in HZ.\r
+ * param srcClock_Hz USART clock source frequency in HZ.\r
* retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
* retval kStatus_Success Set baudrate succeed.\r
* retval kStatus_InvalidArgument One or more arguments are invalid.\r
\r
/* check arguments */\r
assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));\r
- if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))\r
+ if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))\r
{\r
return kStatus_InvalidArgument;\r
}\r
\r
- /*\r
- * Smaller values of OSR can make the sampling position within a data bit less accurate and may\r
- * potentially cause more noise errors or incorrect data.\r
- */\r
- for (osrval = best_osrval; osrval >= 8; osrval--)\r
+ /* If synchronous master mode is enabled, only configure the BRG value. */\r
+ if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)\r
{\r
- brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;\r
- if (brgval > 0xFFFF)\r
+ if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)\r
{\r
- continue;\r
+ brgval = srcClock_Hz / baudrate_Bps;\r
+ base->BRG = brgval - 1U;\r
}\r
- baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));\r
- diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;\r
- if (diff < best_diff)\r
+ }\r
+ else\r
+ {\r
+ /*\r
+ * Smaller values of OSR can make the sampling position within a data bit less accurate and may\r
+ * potentially cause more noise errors or incorrect data.\r
+ */\r
+ for (osrval = best_osrval; osrval >= 8U; osrval--)\r
{\r
- best_diff = diff;\r
- best_osrval = osrval;\r
- best_brgval = brgval;\r
+ brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;\r
+ if (brgval > 0xFFFFU)\r
+ {\r
+ continue;\r
+ }\r
+ baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));\r
+ diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;\r
+ if (diff < best_diff)\r
+ {\r
+ best_diff = diff;\r
+ best_osrval = osrval;\r
+ best_brgval = brgval;\r
+ }\r
}\r
- }\r
\r
- /* value over range */\r
- if (best_brgval > 0xFFFF)\r
- {\r
- return kStatus_USART_BaudrateNotSupport;\r
+ /* value over range */\r
+ if (best_brgval > 0xFFFFU)\r
+ {\r
+ return kStatus_USART_BaudrateNotSupport;\r
+ }\r
+\r
+ base->OSR = best_osrval;\r
+ base->BRG = best_brgval;\r
}\r
\r
- base->OSR = best_osrval;\r
- base->BRG = best_brgval;\r
return kStatus_Success;\r
}\r
\r
return;\r
}\r
/* Check whether txFIFO is enabled */\r
- if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))\r
+ if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))\r
{\r
return;\r
}\r
- for (; length > 0; length--)\r
+ for (; length > 0U; length--)\r
{\r
/* Loop until txFIFO get some space for new data */\r
- while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
+ while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
{\r
}\r
base->FIFOWR = *data;\r
data++;\r
}\r
/* Wait to finish transfer */\r
- while (!(base->STAT & USART_STAT_TXIDLE_MASK))\r
+ while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))\r
{\r
}\r
}\r
*/\r
status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)\r
{\r
- uint32_t status;\r
+ uint32_t statusFlag;\r
+ status_t status = kStatus_Success;\r
\r
/* check arguments */\r
assert(!((NULL == base) || (NULL == data)));\r
}\r
\r
/* Check whether rxFIFO is enabled */\r
- if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))\r
+ if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)\r
{\r
return kStatus_Fail;\r
}\r
- for (; length > 0; length--)\r
+ for (; length > 0U; length--)\r
{\r
/* loop until rxFIFO have some data to read */\r
- while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))\r
+ while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)\r
{\r
}\r
- /* check receive status */\r
- status = base->STAT;\r
- if (status & USART_STAT_FRAMERRINT_MASK)\r
+ /* check rxFIFO statusFlag */\r
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)\r
{\r
- base->STAT |= USART_STAT_FRAMERRINT_MASK;\r
- return kStatus_USART_FramingError;\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
+ status = kStatus_USART_RxError;\r
+ break;\r
}\r
- if (status & USART_STAT_PARITYERRINT_MASK)\r
+ /* check receive statusFlag */\r
+ statusFlag = base->STAT;\r
+ /* Clear all status flags */\r
+ base->STAT |= statusFlag;\r
+ if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)\r
{\r
- base->STAT |= USART_STAT_PARITYERRINT_MASK;\r
- return kStatus_USART_ParityError;\r
+ status = kStatus_USART_ParityError;\r
}\r
- if (status & USART_STAT_RXNOISEINT_MASK)\r
+ if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)\r
{\r
- base->STAT |= USART_STAT_RXNOISEINT_MASK;\r
- return kStatus_USART_NoiseError;\r
+ status = kStatus_USART_FramingError;\r
}\r
- /* check rxFIFO status */\r
- if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)\r
+ if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)\r
{\r
- base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
- base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
- return kStatus_USART_RxError;\r
+ status = kStatus_USART_NoiseError;\r
}\r
\r
- *data = base->FIFORD;\r
- data++;\r
+ if (kStatus_Success == status)\r
+ {\r
+ *data = (uint8_t)base->FIFORD;\r
+ data++;\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
}\r
- return kStatus_Success;\r
+ return status;\r
}\r
\r
/*!\r
usart_transfer_callback_t callback,\r
void *userData)\r
{\r
- int32_t instance = 0;\r
-\r
/* Check 'base' */\r
assert(!((NULL == base) || (NULL == handle)));\r
+\r
+ uint32_t instance = 0;\r
+ usart_to_flexcomm_t handler;\r
+ handler.usart_master_handler = USART_TransferHandleIRQ;\r
+\r
if ((NULL == base) || (NULL == handle))\r
{\r
return kStatus_InvalidArgument;\r
\r
instance = USART_GetInstance(base);\r
\r
- memset(handle, 0, sizeof(*handle));\r
+ (void)memset(handle, 0, sizeof(*handle));\r
/* Set the TX/RX state. */\r
- handle->rxState = kUSART_RxIdle;\r
- handle->txState = kUSART_TxIdle;\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
/* Set the callback and user data. */\r
- handle->callback = callback;\r
- handle->userData = userData;\r
- handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);\r
- handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);\r
+ handle->callback = callback;\r
+ handle->userData = userData;\r
+ handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);\r
+ handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);\r
\r
- FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle);\r
+ FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);\r
\r
/* Enable interrupt in NVIC. */\r
- EnableIRQ(s_usartIRQ[instance]);\r
+ (void)EnableIRQ(s_usartIRQ[instance]);\r
\r
return kStatus_Success;\r
}\r
}\r
/* Check xfer members */\r
assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
- if ((0 == xfer->dataSize) || (NULL == xfer->data))\r
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))\r
{\r
return kStatus_InvalidArgument;\r
}\r
\r
/* Return error if current TX busy. */\r
- if (kUSART_TxBusy == handle->txState)\r
+ if ((uint8_t)kUSART_TxBusy == handle->txState)\r
{\r
return kStatus_USART_TxBusy;\r
}\r
else\r
{\r
- handle->txData = xfer->data;\r
- handle->txDataSize = xfer->dataSize;\r
+ handle->txData = xfer->data;\r
+ handle->txDataSize = xfer->dataSize;\r
handle->txDataSizeAll = xfer->dataSize;\r
- handle->txState = kUSART_TxBusy;\r
+ handle->txState = (uint8_t)kUSART_TxBusy;\r
/* Enable transmiter interrupt. */\r
base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;\r
}\r
assert(NULL != handle);\r
\r
/* Disable interrupts */\r
- USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable);\r
+ USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);\r
/* Empty txFIFO */\r
base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;\r
\r
- handle->txDataSize = 0;\r
- handle->txState = kUSART_TxIdle;\r
+ handle->txDataSize = 0U;\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
}\r
\r
/*!\r
assert(NULL != handle);\r
assert(NULL != count);\r
\r
- if (kUSART_TxIdle == handle->txState)\r
+ if ((uint8_t)kUSART_TxIdle == handle->txState)\r
{\r
return kStatus_NoTransferInProgress;\r
}\r
}\r
/* Check xfer members */\r
assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
- if ((0 == xfer->dataSize) || (NULL == xfer->data))\r
+ if ((0U == xfer->dataSize) || (NULL == xfer->data))\r
{\r
return kStatus_InvalidArgument;\r
}\r
If there are not enough data in ring buffer, copy all of them to xfer->data,\r
save the xfer->data remained empty space to uart handle, receive data\r
to this empty space and trigger callback when finished. */\r
- if (kUSART_RxBusy == handle->rxState)\r
+ if ((uint8_t)kUSART_RxBusy == handle->rxState)\r
{\r
return kStatus_USART_RxBusy;\r
}\r
else\r
{\r
- bytesToReceive = xfer->dataSize;\r
+ bytesToReceive = xfer->dataSize;\r
bytesCurrentReceived = 0U;\r
/* If RX ring buffer is used. */\r
- if (handle->rxRingBuffer)\r
+ if (handle->rxRingBuffer != NULL)\r
{\r
/* Disable IRQ, protect ring buffer. */\r
regPrimask = DisableGlobalIRQ();\r
/* How many bytes in RX ring buffer currently. */\r
bytesToCopy = USART_TransferGetRxRingBufferLength(handle);\r
- if (bytesToCopy)\r
+ if (bytesToCopy != 0U)\r
{\r
bytesToCopy = MIN(bytesToReceive, bytesToCopy);\r
bytesToReceive -= bytesToCopy;\r
{\r
xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];\r
/* Wrap to 0. Not use modulo (%) because it might be large and slow. */\r
- if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
{\r
handle->rxRingBufferTail = 0U;\r
}\r
}\r
}\r
/* If ring buffer does not have enough data, still need to read more data. */\r
- if (bytesToReceive)\r
+ if (bytesToReceive != 0U)\r
{\r
/* No data in ring buffer, save the request to UART handle. */\r
- handle->rxData = xfer->data + bytesCurrentReceived;\r
- handle->rxDataSize = bytesToReceive;\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
handle->rxDataSizeAll = bytesToReceive;\r
- handle->rxState = kUSART_RxBusy;\r
+ handle->rxState = (uint8_t)kUSART_RxBusy;\r
}\r
/* Enable IRQ if previously enabled. */\r
EnableGlobalIRQ(regPrimask);\r
/* Call user callback since all data are received. */\r
- if (0 == bytesToReceive)\r
+ if (0U == bytesToReceive)\r
{\r
- if (handle->callback)\r
+ if (handle->callback != NULL)\r
{\r
handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
}\r
/* Ring buffer not used. */\r
else\r
{\r
- handle->rxData = xfer->data + bytesCurrentReceived;\r
- handle->rxDataSize = bytesToReceive;\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
handle->rxDataSizeAll = bytesToReceive;\r
- handle->rxState = kUSART_RxBusy;\r
+ handle->rxState = (uint8_t)kUSART_RxBusy;\r
\r
/* Enable RX interrupt. */\r
base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;\r
}\r
/* Return the how many bytes have read. */\r
- if (receivedBytes)\r
+ if (receivedBytes != NULL)\r
{\r
*receivedBytes = bytesCurrentReceived;\r
}\r
assert(NULL != handle);\r
\r
/* Only abort the receive to handle->rxData, the RX ring buffer is still working. */\r
- if (!handle->rxRingBuffer)\r
+ if (NULL == handle->rxRingBuffer)\r
{\r
/* Disable interrupts */\r
- USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable);\r
+ USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);\r
/* Empty rxFIFO */\r
base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
}\r
\r
handle->rxDataSize = 0U;\r
- handle->rxState = kUSART_RxIdle;\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
}\r
\r
/*!\r
assert(NULL != handle);\r
assert(NULL != count);\r
\r
- if (kUSART_RxIdle == handle->rxState)\r
+ if ((uint8_t)kUSART_RxIdle == handle->rxState)\r
{\r
return kStatus_NoTransferInProgress;\r
}\r
/* Check arguments */\r
assert((NULL != base) && (NULL != handle));\r
\r
- bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);\r
- bool sendEnabled = handle->txDataSize;\r
+ bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));\r
+ bool sendEnabled = (handle->txDataSize != 0U);\r
+ uint8_t rxdata;\r
+ size_t tmpsize;\r
\r
/* If RX overrun. */\r
- if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)\r
+ if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)\r
{\r
/* Clear rx error state. */\r
base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
/* clear rxFIFO */\r
base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
/* Trigger callback. */\r
- if (handle->callback)\r
+ if (handle->callback != NULL)\r
{\r
handle->callback(base, handle, kStatus_USART_RxError, handle->userData);\r
}\r
}\r
- while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||\r
- (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))\r
+ while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||\r
+ (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))\r
{\r
/* Receive data */\r
- if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))\r
+ if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))\r
{\r
/* Receive to app bufffer if app buffer is present */\r
- if (handle->rxDataSize)\r
+ if (handle->rxDataSize != 0U)\r
{\r
- *handle->rxData = base->FIFORD;\r
+ rxdata = (uint8_t)base->FIFORD;\r
+ *handle->rxData = rxdata;\r
handle->rxDataSize--;\r
handle->rxData++;\r
- receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));\r
- if (!handle->rxDataSize)\r
+ receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));\r
+ if (0U == handle->rxDataSize)\r
{\r
- if (!handle->rxRingBuffer)\r
+ if (NULL == handle->rxRingBuffer)\r
{\r
base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;\r
}\r
- handle->rxState = kUSART_RxIdle;\r
- if (handle->callback)\r
+ handle->rxState = (uint8_t)kUSART_RxIdle;\r
+ if (handle->callback != NULL)\r
{\r
handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
}\r
/* Otherwise receive to ring buffer if ring buffer is present */\r
else\r
{\r
- if (handle->rxRingBuffer)\r
+ if (handle->rxRingBuffer != NULL)\r
{\r
/* If RX ring buffer is full, trigger callback to notify over run. */\r
if (USART_TransferIsRxRingBufferFull(handle))\r
{\r
- if (handle->callback)\r
+ if (handle->callback != NULL)\r
{\r
handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);\r
}\r
}\r
- /* If ring buffer is still full after callback function, the oldest data is overrided. */\r
+ /* If ring buffer is still full after callback function, the oldest data is overridden. */\r
if (USART_TransferIsRxRingBufferFull(handle))\r
{\r
/* Increase handle->rxRingBufferTail to make room for new data. */\r
- if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
{\r
handle->rxRingBufferTail = 0U;\r
}\r
}\r
}\r
/* Read data. */\r
- handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;\r
+ rxdata = (uint8_t)base->FIFORD;\r
+ handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;\r
/* Increase handle->rxRingBufferHead. */\r
- if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)\r
+ if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)\r
{\r
handle->rxRingBufferHead = 0U;\r
}\r
}\r
}\r
/* Send data */\r
- if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
+ if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))\r
{\r
base->FIFOWR = *handle->txData;\r
handle->txDataSize--;\r
handle->txData++;\r
- sendEnabled = handle->txDataSize != 0;\r
+ sendEnabled = handle->txDataSize != 0U;\r
if (!sendEnabled)\r
{\r
base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;\r
- handle->txState = kUSART_TxIdle;\r
- if (handle->callback)\r
- {\r
- handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);\r
- }\r
+ handle->txState = (uint8_t)kUSART_TxIdle;\r
+\r
+ base->INTENSET |= USART_INTENSET_TXIDLEEN_MASK;\r
}\r
}\r
}\r
\r
+ /* Tx idle and the interrupt is enabled. */\r
+ if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) &&\r
+ (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)) && (handle->txState == (uint8_t)kUSART_TxIdle))\r
+ {\r
+ /* Disable tx idle interrupt */\r
+ base->INTENCLR |= USART_INTENCLR_TXIDLECLR_MASK;\r
+ /* Trigger callback. */\r
+ if (handle->callback != NULL)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);\r
+ }\r
+ }\r
+\r
/* ring buffer is not used */\r
if (NULL == handle->rxRingBuffer)\r
{\r
+ tmpsize = handle->rxDataSize;\r
+\r
/* restore if rx transfer ends and rxLevel is different from default value */\r
- if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))\r
+ if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))\r
{\r
base->FIFOTRIG =\r
(base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);\r
}\r
/* decrease level if rx transfer is bellow */\r
- if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))\r
+ if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))\r
{\r
- base->FIFOTRIG =\r
- (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));\r
+ base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));\r
}\r
}\r
}\r
projects / freertos / blobdiff