/*\r
* Copyright (c) 2016, Freescale Semiconductor, Inc.\r
- * Copyright 2016-2018 NXP\r
+ * Copyright 2016-2019 NXP\r
* All rights reserved.\r
*\r
* SPDX-License-Identifier: BSD-3-Clause\r
\r
/*! @name Driver version */\r
/*@{*/\r
-/*! @brief USART driver version 2.0.3. */\r
-#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))\r
+/*! @brief USART driver version 2.1.1. */\r
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))\r
/*@}*/\r
\r
#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)\r
#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)\r
\r
/*! @brief Error codes for the USART driver. */\r
-enum _usart_status\r
+enum\r
{\r
- kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */\r
- kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */\r
- kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */\r
- kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */\r
- kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */\r
- kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */\r
- kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */\r
- kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */\r
- kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */\r
- kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */\r
+ kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */\r
+ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */\r
+ kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */\r
+ kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */\r
+ kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */\r
+ kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */\r
+ kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */\r
+ kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */\r
+ kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */\r
+ kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */\r
kStatus_USART_BaudrateNotSupport =\r
MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */\r
};\r
\r
+/*! @brief USART synchronous mode. */\r
+typedef enum _usart_sync_mode\r
+{\r
+ kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */\r
+ kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */\r
+ kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */\r
+} usart_sync_mode_t;\r
+\r
/*! @brief USART parity mode. */\r
typedef enum _usart_parity_mode\r
{\r
kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */\r
- kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */\r
- kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */\r
+ kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */\r
+ kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */\r
} usart_parity_mode_t;\r
\r
/*! @brief USART stop bit count. */\r
kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */\r
} usart_data_len_t;\r
\r
+/*! @brief USART clock polarity configuration, used in sync mode.*/\r
+typedef enum _usart_clock_polarity\r
+{\r
+ kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */\r
+ kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */\r
+} usart_clock_polarity_t;\r
+\r
/*! @brief txFIFO watermark values */\r
typedef enum _usart_txfifo_watermark\r
{\r
*/\r
enum _usart_flags\r
{\r
- kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */\r
- kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */\r
- kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */\r
- kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */\r
+ kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */\r
+ kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */\r
+ kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */\r
+ kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */\r
kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */\r
- kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */\r
+ kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */\r
};\r
\r
/*! @brief USART configuration structure. */\r
bool loopback; /*!< Enable peripheral loopback */\r
bool enableRx; /*!< Enable RX */\r
bool enableTx; /*!< Enable TX */\r
+ bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */\r
usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */\r
usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */\r
+ usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */\r
+ usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */\r
} usart_config_t;\r
\r
/*! @brief USART transfer structure. */\r
volatile uint8_t txState; /*!< TX transfer state. */\r
volatile uint8_t rxState; /*!< RX transfer state */\r
\r
- usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */\r
- usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */\r
+ uint8_t txWatermark; /*!< txFIFO watermark */\r
+ uint8_t rxWatermark; /*!< rxFIFO watermark */\r
};\r
\r
+/*! @brief Typedef for usart interrupt handler. */\r
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);\r
+\r
/*******************************************************************************\r
* API\r
******************************************************************************/\r
*\r
* @param base USART peripheral base address.\r
* @param baudrate_Bps USART baudrate to be set.\r
- * @param srcClock_Hz USART clock source freqency in HZ.\r
+ * @param srcClock_Hz USART clock source frequency in HZ.\r
* @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
* @retval kStatus_Success Set baudrate succeed.\r
* @retval kStatus_InvalidArgument One or more arguments are invalid.\r
*/\r
static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)\r
{\r
- base->FIFOINTENSET = mask & 0xF;\r
+ base->FIFOINTENSET = mask & 0xFUL;\r
}\r
\r
/*!\r
*/\r
static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)\r
{\r
- base->FIFOINTENCLR = mask & 0xF;\r
+ base->FIFOINTENCLR = mask & 0xFUL;\r
}\r
\r
/*!\r
}\r
\r
/*!\r
-* @brief Enable DMA for Tx\r
-*/\r
+ * @brief Enable DMA for Tx\r
+ */\r
static inline void USART_EnableTxDMA(USART_Type *base, bool enable)\r
{\r
if (enable)\r
}\r
\r
/*!\r
-* @brief Enable DMA for Rx\r
-*/\r
+ * @brief Enable DMA for Rx\r
+ */\r
static inline void USART_EnableRxDMA(USART_Type *base, bool enable)\r
{\r
if (enable)\r
}\r
}\r
\r
+/*!\r
+ * @brief Continuous Clock generation.\r
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.\r
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing\r
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CTL |= USART_CTL_CC_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CTL &= ~USART_CTL_CC_MASK;\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enable Continuous Clock generation bit auto clear.\r
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete\r
+ * character has been received. This bit is cleared at the same time.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable auto clear or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CTL |= USART_CTL_CLRCCONRX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CTL &= ~USART_CTL_CLRCCONRX_MASK;\r
+ }\r
+}\r
/* @} */\r
\r
/*!\r
*/\r
static inline uint8_t USART_ReadByte(USART_Type *base)\r
{\r
- return base->FIFORD;\r
+ return (uint8_t)base->FIFORD;\r
}\r
\r
/*!\r
projects / freertos / blobdiff