//*****************************************************************************\r
// boot_multicore_slave.c\r
//\r
-// Provides functions to boot slave core in LPC55xx multicore system\r
+// Provides simple functions to boot slave core in LPC55xx multicore system\r
//\r
-// Version : 190215\r
+// Version : 181106\r
//\r
//*****************************************************************************\r
//\r
-// Copyright(C) NXP Semiconductors, 2019\r
+// Copyright 2016-2019 NXP\r
// All rights reserved.\r
//\r
-// Software that is described herein is for illustrative purposes only\r
-// which provides customers with programming information regarding the\r
-// LPC products. This software is supplied "AS IS" without any warranties of\r
-// any kind, and NXP Semiconductors and its licensor disclaim any and\r
-// all warranties, express or implied, including all implied warranties of\r
-// merchantability, fitness for a particular purpose and non-infringement of\r
-// intellectual property rights. NXP Semiconductors assumes no responsibility\r
-// or liability for the use of the software, conveys no license or rights under any\r
-// patent, copyright, mask work right, or any other intellectual property rights in\r
-// or to any products. NXP Semiconductors reserves the right to make changes\r
-// in the software without notification. NXP Semiconductors also makes no\r
-// representation or warranty that such application will be suitable for the\r
-// specified use without further testing or modification.\r
-//\r
-// Permission to use, copy, modify, and distribute this software and its\r
-// documentation is hereby granted, under NXP Semiconductors' and its\r
-// licensor's relevant copyrights in the software, without fee, provided that it\r
-// is used in conjunction with NXP Semiconductors microcontrollers. This\r
-// copyright, permission, and disclaimer notice must appear in all copies of\r
-// this code.\r
+// SPDX-License-Identifier: BSD-3-Clause\r
//*****************************************************************************\r
\r
-#if defined (__MULTICORE_MASTER)\r
+#if defined(__MULTICORE_MASTER)\r
\r
#include <stdint.h>\r
\r
-// ==================================================================\r
-// Define registers related to multicore CPU Control and setup\r
-// ==================================================================\r
-#define SYSCON_BASE ((uint32_t) 0x50000000)\r
-#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800)))\r
-#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804)))\r
-#define CPSTACK (((volatile uint32_t *) (SYSCON_BASE + 0x808)))\r
-#define CPSTAT (((volatile uint32_t *) (SYSCON_BASE + 0x80C)))\r
-#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))\r
-#define CORE1_CLK_ENA (1<<3)\r
-#define CORE1_RESET_ENA (1<<5)\r
+//#define SYSCON_BASE ((uint32_t) 0x40000000)\r
+#define SYSCON_BASE ((uint32_t)0x50000000)\r
\r
+#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))\r
+#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))\r
+#define CPUCFG (((volatile uint32_t *)(SYSCON_BASE + 0xFD4)))\r
\r
-// ==================================================================\r
-// Function to boot the slave (core 1)\r
-// ==================================================================\r
-void slave_core1_boot(uint32_t *coentry, uint32_t *costackptr) {\r
+#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))\r
+#define CORE1_CLK_ENA (1 << 3)\r
+#define CORE1_RESET_ENA (1 << 5)\r
+#define CORE1_ENABLE (1 << 2)\r
\r
- volatile uint32_t *u32REG, u32Val;\r
+extern uint8_t __core_m33slave_START__;\r
\r
- // Load the slave's stack pointer value\r
- *CPSTACK = (uint32_t) costackptr;\r
- // Load address of the slave code in memory (for slave's VTOR)\r
- *CPBOOT = (uint32_t) coentry;\r
+void boot_multicore_slave(void)\r
+{\r
+ volatile uint32_t *u32REG, u32Val;\r
\r
- // Read CPU control register and update to start slave execution\r
- u32REG = (uint32_t *) CPUCTRL;\r
- u32Val = *u32REG;\r
- // Enable slave clock and reset\r
- u32Val |= (CPUCTRL_KEY | ((CORE1_CLK_ENA | CORE1_RESET_ENA) & 0x7F));\r
- *u32REG = u32Val;\r
- // Clear slave reset\r
- u32Val &= ~CORE1_RESET_ENA;\r
- *u32REG = u32Val;\r
- // Slave is now executing\r
-}\r
-\r
-// ==================================================================\r
-// Address of slave code in memory - provided by linker script\r
-extern uint8_t __core_m33slave_START__;\r
-// ==================================================================\r
+ unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__;\r
\r
-// ==================================================================\r
-// Top level function to boot the slave core\r
-// ==================================================================\r
-void boot_multicore_slave(void) {\r
+ // Enable CPU1 in SYSCON->CPUCFG\r
+ *CPUCFG |= CORE1_ENABLE;\r
\r
- // Get the address of the slave code in memory\r
- uint32_t *slavevectortable_ptr = (uint32_t *)&__core_m33slave_START__;\r
+ // Set CPU1 boot address in SYSCON->CPBoot\r
+ *CPBOOT = (uint32_t)slavevectortable_ptr;\r
\r
- // Get initial address for slave's stack pointer\r
- volatile unsigned int spaddr;\r
- spaddr = *slavevectortable_ptr;\r
+ // Read SYSCON->CPUCTRL and set key value in bits 31:16\r
+ u32REG = (uint32_t *)CPUCTRL;\r
+ u32Val = *u32REG | CPUCTRL_KEY;\r
\r
- // Boot the slave - passing address of code and stack pointer\r
- slave_core1_boot(slavevectortable_ptr, (uint32_t *)spaddr);\r
+ // Enable slave clock and reset in SYSCON->CPUCTRL\r
+ *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA;\r
\r
+ // Clear slave reset in SYSCON->CPUCTRL\r
+ *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA);\r
}\r
-#endif //defined (__MULTICORE_MASTER)\r
+#endif // defined (__MULTICORE_MASTER)\r
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