--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv7.h\r
+ * @brief CMSIS MPU API for Armv7-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+ \r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+ \r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
+\r
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only\r
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only\r
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \\r
+ ((Region) & MPU_RBAR_REGION_Msk) | \\r
+ (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Memory Access Attributes\r
+* \r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+*/ \r
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \\r
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \\r
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \\r
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \\r
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/\r
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \\r
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \\r
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \\r
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\r
+ \r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/ \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
+\r
+/**\r
+* MPU Memory Access Attribute for strongly ordered memory.\r
+* - TEX: 000b\r
+* - Shareable\r
+* - Non-cacheable\r
+* - Non-bufferable\r
+*/ \r
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
+\r
+/**\r
+* MPU Memory Access Attribute for device memory.\r
+* - TEX: 000b (if non-shareable) or 010b (if shareable)\r
+* - Shareable or non-shareable\r
+* - Non-cacheable\r
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
+*\r
+* \param IsShareable Configures the device memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
+\r
+/**\r
+* MPU Memory Access Attribute for normal memory.\r
+* - TEX: 1BBb (reflecting outer cacheability rules)\r
+* - Shareable or non-shareable\r
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
+*\r
+* \param OuterCp Configures the outer cache policy.\r
+* \param InnerCp Configures the inner cache policy.\r
+* \param IsShareable Configures the memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
+\r
+/**\r
+* MPU Memory Access Attribute non-cacheable policy.\r
+*/\r
+#define ARM_MPU_CACHEP_NOCACHE 0U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, write and read allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_WRA 1U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-through, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WT_NWA 2U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_NWA 3U\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; //!< The region base address register value (RBAR)\r
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ while (cnt > MPU_TYPE_RALIASES) {\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+ table += MPU_TYPE_RALIASES;\r
+ cnt -= MPU_TYPE_RALIASES;\r
+ }\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
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