--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_dfsdm.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DFSDM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32L4xx_HAL_DFSDM_H\r
+#define STM32L4xx_HAL_DFSDM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \\r
+ defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DFSDM\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL DFSDM Channel states definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */\r
+ HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */\r
+ HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */\r
+} HAL_DFSDM_Channel_StateTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel output clock structure definition\r
+ */\r
+typedef struct\r
+{\r
+ FunctionalState Activation; /*!< Output clock enable/disable */\r
+ uint32_t Selection; /*!< Output clock is system clock or audio clock.\r
+ This parameter can be a value of @ref DFSDM_Channel_OuputClock */\r
+ uint32_t Divider; /*!< Output clock divider.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 256 */\r
+} DFSDM_Channel_OutputClockTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel input structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.\r
+ ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,\r
+ STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,\r
+ STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.\r
+ This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */\r
+ uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.\r
+ This parameter can be a value of @ref DFSDM_Channel_DataPacking */\r
+ uint32_t Pins; /*!< Input pins are taken from same or following channel.\r
+ This parameter can be a value of @ref DFSDM_Channel_InputPins */\r
+} DFSDM_Channel_InputTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel serial interface structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Type; /*!< SPI or Manchester modes.\r
+ This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */\r
+ uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).\r
+ This parameter can be a value of @ref DFSDM_Channel_SpiClock */\r
+} DFSDM_Channel_SerialInterfaceTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel analog watchdog structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.\r
+ This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */\r
+ uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r
+} DFSDM_Channel_AwdTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */\r
+ DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */\r
+ DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */\r
+ DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */\r
+ int32_t Offset; /*!< DFSDM channel offset.\r
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+ uint32_t RightBitShift; /*!< DFSDM channel right bit shift.\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
+} DFSDM_Channel_InitTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel handle structure definition\r
+ */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+typedef struct __DFSDM_Channel_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+{\r
+ DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */\r
+ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */\r
+ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+ void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */\r
+ void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */\r
+ void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */\r
+ void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */\r
+#endif\r
+} DFSDM_Channel_HandleTypeDef;\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief DFSDM channel callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */\r
+ HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */\r
+ HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */\r
+ HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */\r
+} HAL_DFSDM_Channel_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel callback pointer definition\r
+ */\r
+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+#endif\r
+\r
+/**\r
+ * @brief HAL DFSDM Filter states definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */\r
+ HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */\r
+ HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */\r
+ HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */\r
+ HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */\r
+ HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */\r
+} HAL_DFSDM_Filter_StateTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter regular conversion parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.\r
+ This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
+ FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */\r
+ FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */\r
+} DFSDM_Filter_RegularParamTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter injected conversion parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.\r
+ This parameter can be a value of @ref DFSDM_Filter_Trigger */\r
+ FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */\r
+ FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */\r
+ uint32_t ExtTrigger; /*!< External trigger.\r
+ This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */\r
+ uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.\r
+ This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */\r
+} DFSDM_Filter_InjectedParamTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SincOrder; /*!< Sinc filter order.\r
+ This parameter can be a value of @ref DFSDM_Filter_SincOrder */\r
+ uint32_t Oversampling; /*!< Filter oversampling ratio.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r
+ uint32_t IntOversampling; /*!< Integrator oversampling ratio.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 256 */\r
+} DFSDM_Filter_FilterParamTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter init structure definition\r
+ */\r
+typedef struct\r
+{\r
+ DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */\r
+ DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */\r
+ DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */\r
+} DFSDM_Filter_InitTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter handle structure definition\r
+ */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+typedef struct __DFSDM_Filter_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */\r
+{\r
+ DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */\r
+ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */\r
+ DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */\r
+ DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */\r
+ uint32_t RegularContMode; /*!< Regular conversion continuous mode */\r
+ uint32_t RegularTrigger; /*!< Trigger used for regular conversion */\r
+ uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */\r
+ uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */\r
+ FunctionalState InjectedScanMode; /*!< Injected scanning mode */\r
+ uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */\r
+ uint32_t InjConvRemaining; /*!< Injected conversions remaining */\r
+ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */\r
+ uint32_t ErrorCode; /*!< DFSDM filter error code */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+ void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */\r
+ void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */\r
+ void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */\r
+ void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */\r
+ void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */\r
+ void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */\r
+ void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */\r
+ void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */\r
+#endif\r
+} DFSDM_Filter_HandleTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter analog watchdog parameters structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.\r
+ This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */\r
+ uint32_t Channel; /*!< Analog watchdog channel selection.\r
+ This parameter can be a values combination of @ref DFSDM_Channel_Selection */\r
+ int32_t HighThreshold; /*!< High threshold for the analog watchdog.\r
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+ int32_t LowThreshold; /*!< Low threshold for the analog watchdog.\r
+ This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r
+ uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.\r
+ This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
+ uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.\r
+ This parameter can be a values combination of @ref DFSDM_BreakSignals */\r
+} DFSDM_Filter_AwdParamTypeDef;\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief DFSDM filter callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */\r
+ HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */\r
+ HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */\r
+ HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */\r
+ HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */\r
+ HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */\r
+ HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */\r
+} HAL_DFSDM_Filter_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief DFSDM filter callback pointer definition\r
+ */\r
+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */\r
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+ defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */\r
+#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */\r
+#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */\r
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */\r
+#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */\r
+#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */\r
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */\r
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order\r
+ * @{\r
+ */\r
+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */\r
+#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */\r
+#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */\r
+#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger\r
+ * @{\r
+ */\r
+#define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */\r
+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */\r
+#define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger\r
+ * @{\r
+ */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \\r
+ DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
+ DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \\r
+ DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */\r
+#else\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */\r
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge\r
+ * @{\r
+ */\r
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */\r
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */\r
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order\r
+ * @{\r
+ */\r
+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */\r
+#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */\r
+#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */\r
+#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */\r
+#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */\r
+#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source\r
+ * @{\r
+ */\r
+#define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */\r
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code\r
+ * @{\r
+ */\r
+#define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */\r
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */\r
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */\r
+#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_BreakSignals DFSDM break signals\r
+ * @{\r
+ */\r
+#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */\r
+#define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */\r
+#define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */\r
+#define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */\r
+#define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection\r
+ * @{\r
+ */\r
+/* DFSDM Channels ------------------------------------------------------------*/\r
+/* The DFSDM channels are defined as follows:\r
+ - in 16-bit LSB the channel mask is set\r
+ - in 16-bit MSB the channel number is set\r
+ e.g. for channel 5 definition:\r
+ - the channel mask is 0x00000020 (bit 5 is set)\r
+ - the channel number 5 is 0x00050000\r
+ --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define DFSDM_CHANNEL_0 0x00000001U\r
+#define DFSDM_CHANNEL_1 0x00010002U\r
+#define DFSDM_CHANNEL_2 0x00020004U\r
+#define DFSDM_CHANNEL_3 0x00030008U\r
+#else\r
+#define DFSDM_CHANNEL_0 0x00000001U\r
+#define DFSDM_CHANNEL_1 0x00010002U\r
+#define DFSDM_CHANNEL_2 0x00020004U\r
+#define DFSDM_CHANNEL_3 0x00030008U\r
+#define DFSDM_CHANNEL_4 0x00040010U\r
+#define DFSDM_CHANNEL_5 0x00050020U\r
+#define DFSDM_CHANNEL_6 0x00060040U\r
+#define DFSDM_CHANNEL_7 0x00070080U\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode\r
+ * @{\r
+ */\r
+#define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */\r
+#define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold\r
+ * @{\r
+ */\r
+#define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */\r
+#define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset DFSDM channel handle state.\r
+ * @param __HANDLE__ DFSDM channel handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)\r
+#endif\r
+\r
+/** @brief Reset DFSDM filter handle state.\r
+ * @param __HANDLE__ DFSDM filter handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+/* Include DFSDM HAL Extension module */\r
+#include "stm32l4xx_hal_dfsdm_ex.h"\r
+#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Channel initialization and de-initialization functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/* Channel callbacks register/unregister functions ****************************/\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,\r
+ pDFSDM_Channel_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r
+ * @{\r
+ */\r
+/* Channel operation functions ************************************************/\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+\r
+int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r
+\r
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r
+ * @{\r
+ */\r
+/* Channel state function *****************************************************/\r
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Filter initialization and de-initialization functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)\r
+/* Filter callbacks register/unregister functions ****************************/\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,\r
+ pDFSDM_Filter_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ pDFSDM_Filter_AwdCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r
+ * @{\r
+ */\r
+/* Filter control functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel,\r
+ uint32_t ContinuousMode);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r
+ * @{\r
+ */\r
+/* Filter operation functions *********************/\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r
+ DFSDM_Filter_AwdParamTypeDef *awdParam);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);\r
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r
+\r
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r
+ * @{\r
+ */\r
+/* Filter state functions *****************************************************/\r
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros\r
+* @{\r
+*/\r
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \\r
+ ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))\r
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \\r
+ defined(STM32L496xx) || defined(STM32L4A6xx) || \\r
+ defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
+ ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \\r
+ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
+#else\r
+#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\r
+ ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
+/* STM32L496xx || STM32L4A6xx || */\r
+/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \\r
+ ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \\r
+ ((MODE) == DFSDM_CHANNEL_DUAL_MODE))\r
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \\r
+ ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))\r
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \\r
+ ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \\r
+ ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \\r
+ ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))\r
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \\r
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \\r
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \\r
+ ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))\r
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \\r
+ ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \\r
+ ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \\r
+ ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))\r
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))\r
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)\r
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)\r
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
+ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))\r
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\r
+ ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
+#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))\r
+#else\r
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \\r
+ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \\r
+ ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \\r
+ ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))\r
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \\r
+ ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \\r
+ ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \\r
+ ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \\r
+ ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \\r
+ ((ORDER) == DFSDM_FILTER_SINC5_ORDER))\r
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))\r
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))\r
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \\r
+ ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))\r
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r
+#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)\r
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)\r
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_1) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_2) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_3))\r
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))\r
+#else\r
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_1) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_2) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_3) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_4) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_5) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_6) || \\r
+ ((CHANNEL) == DFSDM_CHANNEL_7))\r
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx */\r
+#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \\r
+ ((MODE) == DFSDM_CONTINUOUS_CONV_ON))\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */\r
+/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
+/* STM32L496xx || STM32L4A6xx || */\r
+/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32L4xx_HAL_DFSDM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff