--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_flash_ramfunc.c\r
+ * @author MCD Application Team\r
+ * @brief FLASH RAMFUNC driver.\r
+ * This file provides a Flash firmware functions which should be\r
+ * executed from internal SRAM\r
+ * + FLASH HalfPage Programming\r
+ * + FLASH Power Down in Run mode\r
+ *\r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### Flash RAM functions #####\r
+ ==============================================================================\r
+\r
+ *** ARM Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using the toolchain options.\r
+ Functions that are executed in RAM should reside in a separate\r
+ source module. Using the 'Options for File' dialog you can simply change\r
+ the 'Code / Const' area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the\r
+ Options for Target' dialog.\r
+\r
+ *** ICCARM Compiler ***\r
+ -----------------------\r
+ [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".\r
+\r
+ *** GNU Compiler ***\r
+ --------------------\r
+ [..] RAM functions are defined using a specific toolchain attribute\r
+ "__attribute__((section(".RamFunc")))".\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC\r
+ * @brief FLASH functions executed from RAM\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+extern FLASH_ProcessTypeDef pFlash;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions -------------------------------------------------------*/\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### ramfunc functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions that should be executed from RAM.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable the Power down in Run Mode\r
+ * @note This function should be called and executed from SRAM memory\r
+ * @retval None\r
+ */\r
+__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)\r
+{\r
+ /* Enable the Power Down in Run mode*/\r
+ __HAL_FLASH_POWER_DOWN_ENABLE();\r
+\r
+ return HAL_OK;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power down in Run Mode\r
+ * @note This function should be called and executed from SRAM memory\r
+ * @retval None\r
+ */\r
+__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)\r
+{\r
+ /* Disable the Power Down in Run mode*/\r
+ __HAL_FLASH_POWER_DOWN_DISABLE();\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+/**\r
+ * @brief Program the FLASH DBANK User Option Byte.\r
+ *\r
+ * @note To configure the user option bytes, the option lock bit OPTLOCK must\r
+ * be cleared with the call of the HAL_FLASH_OB_Unlock() function.\r
+ * @note To modify the DBANK option byte, no PCROP region should be defined.\r
+ * To deactivate PCROP, user should perform RDP changing\r
+ *\r
+ * @param DBankConfig: The FLASH DBANK User Option Byte value.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data\r
+ * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data\r
+ *\r
+ * @retval HAL status\r
+ */\r
+__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)\r
+{\r
+ register uint32_t count, reg;\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check if the PCROP is disabled */\r
+ reg = FLASH->PCROP1SR;\r
+ if (reg > FLASH->PCROP1ER)\r
+ {\r
+ reg = FLASH->PCROP2SR;\r
+ if (reg > FLASH->PCROP2ER)\r
+ {\r
+ /* Disable Flash prefetch */\r
+ __HAL_FLASH_PREFETCH_BUFFER_DISABLE();\r
+\r
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)\r
+ {\r
+ /* Disable Flash instruction cache */\r
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\r
+\r
+ /* Flush Flash instruction cache */\r
+ __HAL_FLASH_INSTRUCTION_CACHE_RESET();\r
+ }\r
+\r
+ if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)\r
+ {\r
+ /* Disable Flash data cache */\r
+ __HAL_FLASH_DATA_CACHE_DISABLE();\r
+\r
+ /* Flush Flash data cache */\r
+ __HAL_FLASH_DATA_CACHE_RESET();\r
+ }\r
+\r
+ /* Disable WRP zone 1 of 1st bank if needed */\r
+ reg = FLASH->WRP1AR;\r
+ if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=\r
+ ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))\r
+ {\r
+ MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);\r
+ }\r
+\r
+ /* Disable WRP zone 2 of 1st bank if needed */\r
+ reg = FLASH->WRP1BR;\r
+ if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=\r
+ ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))\r
+ {\r
+ MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);\r
+ }\r
+\r
+ /* Disable WRP zone 1 of 2nd bank if needed */\r
+ reg = FLASH->WRP2AR;\r
+ if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=\r
+ ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))\r
+ {\r
+ MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);\r
+ }\r
+\r
+ /* Disable WRP zone 2 of 2nd bank if needed */\r
+ reg = FLASH->WRP2BR;\r
+ if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=\r
+ ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))\r
+ {\r
+ MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);\r
+ }\r
+\r
+ /* Modify the DBANK user option byte */\r
+ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);\r
+\r
+ /* Set OPTSTRT Bit */\r
+ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+ /* Wait for last operation to be completed */\r
+ /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */\r
+ count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);\r
+ do\r
+ {\r
+ if (count == 0U)\r
+ {\r
+ break;\r
+ }\r
+ count--;\r
+ } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);\r
+\r
+ /* If the option byte program operation is completed, disable the OPTSTRT Bit */\r
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);\r
+\r
+ /* Set the bit to force the option byte reloading */\r
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
+\r
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