--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization/de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Defines PWR Private Defines\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */\r
+#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enable access to the backup domain\r
+ * (RTC registers, RTC backup data registers).\r
+ * @note After reset, the backup domain is protected against\r
+ * possible unwanted write accesses.\r
+ * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.\r
+ * In order to set or modify the RTC clock, the backup domain access must be\r
+ * disabled.\r
+ * @note LSEON bit that switches on and off the LSE crystal belongs as well to the\r
+ * back-up domain.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disable access to the backup domain\r
+ * (RTC registers, RTC backup data registers).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Low Power modes configuration functions\r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+\r
+ [..]\r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a\r
+ threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).\r
+\r
+ (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower\r
+ than the PVD threshold. This event is internally connected to the EXTI\r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+\r
+ *** WakeUp pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.\r
+ The polarity of these pins can be set to configure event detection on high\r
+ level (rising edge) or low level (falling edge).\r
+\r
+\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The devices feature 8 low-power modes:\r
+ (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.\r
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.\r
+ (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.\r
+ (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.\r
+ (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.\r
+ (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.\r
+ (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.\r
+ (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.\r
+ (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.\r
+\r
+\r
+ *** Low-power run mode ***\r
+ ==========================\r
+ [..]\r
+ (+) Entry: (from main run mode)\r
+ (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.\r
+\r
+ (+) Exit:\r
+ (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only\r
+ then can the system clock frequency be increased above 2 MHz.\r
+\r
+\r
+ *** Sleep mode / Low-power sleep mode ***\r
+ =========================================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API\r
+ in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.\r
+ (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).\r
+ (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).\r
+ In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+\r
+ (+) WFI Exit:\r
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt\r
+ controller (NVIC) or any wake-up event.\r
+\r
+ (+) WFE Exit:\r
+ (++) Any wake-up event such as an EXTI line configured in event mode.\r
+\r
+ [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,\r
+ the MCU is in Low-power Run mode.\r
+\r
+ *** Stop 0, Stop 1 and Stop 2 modes ***\r
+ ===============================\r
+ [..]\r
+ (+) Entry:\r
+ The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:\r
+ (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().\r
+ (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.\r
+ (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):\r
+ (++) PWR_MAINREGULATOR_ON\r
+ (++) PWR_LOWPOWERREGULATOR_ON\r
+ (+) Exit (interrupt or event-triggered, specified when entering STOP mode):\r
+ (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction\r
+ (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction\r
+\r
+ (+) WFI Exit:\r
+ (++) Any EXTI Line (Internal or External) configured in Interrupt mode.\r
+ (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts\r
+ when programmed in wakeup mode.\r
+ (+) WFE Exit:\r
+ (++) Any EXTI Line (Internal or External) configured in Event mode.\r
+\r
+ [..]\r
+ When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode\r
+ depending on the LPR bit setting.\r
+ When exiting Stop 2 mode, the MCU is in Run mode.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ The Standby mode offers two options:\r
+ (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).\r
+ SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers\r
+ and Standby circuitry.\r
+ (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).\r
+ SRAM and register contents are lost except for the RTC registers, RTC backup registers\r
+ and Standby circuitry.\r
+\r
+ (++) Entry:\r
+ (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.\r
+ SRAM1 and register contents are lost except for registers in the Backup domain and\r
+ Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
+ To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
+ to set RRS bit.\r
+\r
+ (++) Exit:\r
+ (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
+ external reset in NRST pin, IWDG reset.\r
+\r
+ [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.\r
+\r
+\r
+ *** Shutdown mode ***\r
+ ======================\r
+ [..]\r
+ In Shutdown mode,\r
+ voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.\r
+ SRAM and registers contents are lost except for backup domain registers.\r
+\r
+ (+) Entry:\r
+ The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.\r
+\r
+ (+) Exit:\r
+ (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,\r
+ external reset in NRST pin.\r
+\r
+ [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.\r
+\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC\r
+ Wakeup event, a tamper event or a time-stamp event, without depending on\r
+ an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes\r
+\r
+\r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to\r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it\r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+\r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+\r
+/**\r
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).\r
+ * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD\r
+ * configuration information.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage thresholds corresponding to each\r
+ * detection level.\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+\r
+ /* Set PLS bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);\r
+\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable the Power Voltage Detector (PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_CR2_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Detector (PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values which set the default polarity\r
+ * i.e. detection on high level (rising edge):\r
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
+ *\r
+ * or one of the following value where the user can explicitly specify the enabled pin and\r
+ * the chosen polarity:\r
+ * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW\r
+ * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW\r
+ * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW\r
+ * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW\r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+\r
+ /* Specifies the Wake-Up pin polarity for the event detection\r
+ (rising or falling edge) */\r
+ MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));\r
+\r
+ /* Enable wake-up pin */\r
+ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));\r
+\r
+\r
+}\r
+\r
+/**\r
+ * @brief Disable the WakeUp PINx functionality.\r
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enter Sleep or Low-power Sleep mode.\r
+ * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)\r
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)\r
+ * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet\r
+ * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set\r
+ * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
+ * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.\r
+ * Additionally, the clock frequency must be reduced below 2 MHz.\r
+ * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
+ * be done before calling HAL_PWR_EnterSLEEPMode() API.\r
+ * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in\r
+ * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.\r
+ * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction\r
+ * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction\r
+ * @note When WFI entry is used, tick interrupt have to be disabled if not desired as\r
+ * the interrupt wake up source.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Set Regulator parameter */\r
+ if (Regulator == PWR_MAINREGULATOR_ON)\r
+ {\r
+ /* If in low-power run mode at this point, exit it */\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
+ {\r
+ if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)\r
+ {\r
+ return ;\r
+ }\r
+ }\r
+ /* Regulator now in main mode. */\r
+ }\r
+ else\r
+ {\r
+ /* If in run mode, first move to low-power run mode.\r
+ The system clock frequency must be below 2 MHz at this point. */\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)\r
+ {\r
+ HAL_PWREx_EnableLowPowerRunMode();\r
+ }\r
+ }\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enter Stop mode\r
+ * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running\r
+ * on devices where only "Stop mode" is mentioned with main or low power regulator ON.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+ * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+ * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+ * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+ * only to the peripheral requesting it.\r
+ * SRAM1, SRAM2 and register contents are preserved.\r
+ * The BOR is available.\r
+ * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).\r
+ * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+ * is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+ * @note When the voltage regulator operates in low power mode (Stop 1), an additional\r
+ * startup delay is incurred when waking up.\r
+ * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption\r
+ * is higher although the startup time is reduced.\r
+ * @param Regulator: Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)\r
+ * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)\r
+ * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.\r
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+\r
+ if(Regulator == PWR_LOWPOWERREGULATOR_ON)\r
+ {\r
+ HAL_PWREx_EnterSTOP1Mode(STOPEntry);\r
+ }\r
+ else\r
+ {\r
+ HAL_PWREx_EnterSTOP0Mode(STOPEntry);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enter Standby mode.\r
+ * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched\r
+ * off. The voltage regulator is disabled, except when SRAM2 content is preserved\r
+ * in which case the regulator is in low-power mode.\r
+ * SRAM1 and register contents are lost except for registers in the Backup domain and\r
+ * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.\r
+ * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API\r
+ * to set RRS bit.\r
+ * The BOR is available.\r
+ * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
+ * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and\r
+ * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the\r
+ * same.\r
+ * These states are effective in Standby mode only if APC bit is set through\r
+ * HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Set Stand-by mode */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.\r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.\r
+ * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor\r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable CORTEX M4 SEVONPEND bit.\r
+ * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable CORTEX M4 SEVONPEND bit.\r
+ * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes\r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ the HAL_PWR_PVDCallback can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff