--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Extended Initialization and de-initialization functions\r
+ * + Extended Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)\r
+#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
+#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)\r
+#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */\r
+#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)\r
+#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */\r
+#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */\r
+#endif\r
+\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
+#define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */\r
+#endif\r
+\r
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask\r
+ * @{\r
+ */\r
+#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */\r
+#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */\r
+#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */\r
+#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value\r
+ * @{\r
+ */\r
+#define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended Peripheral Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Return Voltage Scaling Range.\r
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2\r
+ * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+#if defined(PWR_CR5_R1MODE)\r
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+ {\r
+ return PWR_REGULATOR_VOLTAGE_SCALE2;\r
+ }\r
+ else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)\r
+ {\r
+ /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */\r
+ return PWR_REGULATOR_VOLTAGE_SCALE1;\r
+ }\r
+ else\r
+ {\r
+ return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;\r
+ }\r
+#else\r
+ return (PWR->CR1 & PWR_CR1_VOS);\r
+#endif\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Configure the main internal regulator output voltage.\r
+ * @param VoltageScaling: specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ @if STM32L4S9xx\r
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,\r
+ * typical output voltage at 1.2 V,\r
+ * system frequency up to 120 MHz.\r
+ @endif\r
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,\r
+ * typical output voltage at 1.2 V,\r
+ * system frequency up to 80 MHz.\r
+ * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.0 V,\r
+ * system frequency up to 26 MHz.\r
+ * @note When moving from Range 1 to Range 2, the system frequency must be decreased to\r
+ * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.\r
+ * When moving from Range 2 to Range 1, the system frequency can be increased to\r
+ * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For\r
+ * some devices, the system frequency can be increased up to 120 MHz.\r
+ * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be\r
+ * cleared before returning the status. If the flag is not cleared within\r
+ * 50 microseconds, HAL_TIMEOUT status is reported.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ uint32_t wait_loop_index;\r
+\r
+ assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));\r
+\r
+#if defined(PWR_CR5_R1MODE)\r
+ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)\r
+ {\r
+ /* If current range is range 2 */\r
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+ {\r
+ /* Make sure Range 1 Boost is enabled */\r
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+\r
+ /* Set Range 1 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ /* Wait until VOSF is cleared */\r
+ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+ {\r
+ wait_loop_index--;\r
+ }\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* If current range is range 1 normal or boost mode */\r
+ else\r
+ {\r
+ /* Enable Range 1 Boost (no issue if bit already reset) */\r
+ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+ }\r
+ }\r
+ else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
+ {\r
+ /* If current range is range 2 */\r
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)\r
+ {\r
+ /* Make sure Range 1 Boost is disabled */\r
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+\r
+ /* Set Range 1 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ /* Wait until VOSF is cleared */\r
+ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;\r
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+ {\r
+ wait_loop_index--;\r
+ }\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ /* If current range is range 1 normal or boost mode */\r
+ else\r
+ {\r
+ /* Disable Range 1 Boost (no issue if bit already set) */\r
+ SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set Range 2 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
+ /* No need to wait for VOSF to be cleared for this transition */\r
+ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */\r
+ }\r
+\r
+#else\r
+\r
+ /* If Set Range 1 */\r
+ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)\r
+ {\r
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)\r
+ {\r
+ /* Set Range 1 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);\r
+\r
+ /* Wait until VOSF is cleared */\r
+ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))\r
+ {\r
+ wait_loop_index--;\r
+ }\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)\r
+ {\r
+ /* Set Range 2 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);\r
+ /* No need to wait for VOSF to be cleared for this transition */\r
+ }\r
+ }\r
+#endif\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable battery charging.\r
+ * When VDD is present, charge the external battery on VBAT thru an internal resistor.\r
+ * @param ResistorSelection: specifies the resistor impedance.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor\r
+ * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)\r
+{\r
+ assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));\r
+\r
+ /* Specify resistor selection */\r
+ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);\r
+\r
+ /* Enable battery charging */\r
+ SET_BIT(PWR->CR4, PWR_CR4_VBE);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable battery charging.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableBatteryCharging(void)\r
+{\r
+ CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);\r
+}\r
+\r
+\r
+#if defined(PWR_CR2_USV)\r
+/**\r
+ * @brief Enable VDDUSB supply.\r
+ * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableVddUSB(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_CR2_USV);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable VDDUSB supply.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableVddUSB(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_CR2_USV);\r
+}\r
+#endif /* PWR_CR2_USV */\r
+\r
+#if defined(PWR_CR2_IOSV)\r
+/**\r
+ * @brief Enable VDDIO2 supply.\r
+ * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableVddIO2(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_CR2_IOSV);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable VDDIO2 supply.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableVddIO2(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);\r
+}\r
+#endif /* PWR_CR2_IOSV */\r
+\r
+\r
+/**\r
+ * @brief Enable Internal Wake-up Line.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableInternalWakeUpLine(void)\r
+{\r
+ SET_BIT(PWR->CR3, PWR_CR3_EIWF);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable Internal Wake-up Line.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableInternalWakeUpLine(void)\r
+{\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable GPIO pull-up state in Standby and Shutdown modes.\r
+ * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in\r
+ * pull-up state in Standby and Shutdown modes.\r
+ * @note This state is effective in Standby and Shutdown modes only if APC bit\r
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+ * @note The configuration is lost when exiting the Shutdown mode due to the\r
+ * power-on reset, maintained when exiting the Standby mode.\r
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
+ * PDy bit of PWR_PDCRx register is cleared unless it is reserved.\r
+ * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input\r
+ * parameter at the same time are set.\r
+ * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
+ * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+ * @param GPIONumber: Specify the I/O pins numbers.\r
+ * This parameter can be one of the following values:\r
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+ * I/O pins are available) or the logical OR of several of them to set\r
+ * several bits for a given port in a single API call.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ assert_param(IS_PWR_GPIO(GPIO));\r
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+ switch (GPIO)\r
+ {\r
+ case PWR_GPIO_A:\r
+ SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+ CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+ break;\r
+ case PWR_GPIO_B:\r
+ SET_BIT(PWR->PUCRB, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+ break;\r
+ case PWR_GPIO_C:\r
+ SET_BIT(PWR->PUCRC, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
+ break;\r
+#if defined(GPIOD)\r
+ case PWR_GPIO_D:\r
+ SET_BIT(PWR->PUCRD, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOE)\r
+ case PWR_GPIO_E:\r
+ SET_BIT(PWR->PUCRE, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOF)\r
+ case PWR_GPIO_F:\r
+ SET_BIT(PWR->PUCRF, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOG)\r
+ case PWR_GPIO_G:\r
+ SET_BIT(PWR->PUCRG, GPIONumber);\r
+ CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
+ break;\r
+#endif\r
+ case PWR_GPIO_H:\r
+ SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+ CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+ CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+ break;\r
+#if defined(GPIOI)\r
+ case PWR_GPIO_I:\r
+ SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ break;\r
+#endif\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.\r
+ * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O\r
+ * in pull-up state in Standby and Shutdown modes.\r
+ * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input\r
+ * parameter at the same time are reset.\r
+ * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H\r
+ * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+ * @param GPIONumber: Specify the I/O pins numbers.\r
+ * This parameter can be one of the following values:\r
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+ * I/O pins are available) or the logical OR of several of them to reset\r
+ * several bits for a given port in a single API call.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ assert_param(IS_PWR_GPIO(GPIO));\r
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+ switch (GPIO)\r
+ {\r
+ case PWR_GPIO_A:\r
+ CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+ break;\r
+ case PWR_GPIO_B:\r
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
+ break;\r
+ case PWR_GPIO_C:\r
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
+ break;\r
+#if defined(GPIOD)\r
+ case PWR_GPIO_D:\r
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOE)\r
+ case PWR_GPIO_E:\r
+ CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOF)\r
+ case PWR_GPIO_F:\r
+ CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOG)\r
+ case PWR_GPIO_G:\r
+ CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
+ break;\r
+#endif\r
+ case PWR_GPIO_H:\r
+ CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+ break;\r
+#if defined(GPIOI)\r
+ case PWR_GPIO_I:\r
+ CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ break;\r
+#endif\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable GPIO pull-down state in Standby and Shutdown modes.\r
+ * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in\r
+ * pull-down state in Standby and Shutdown modes.\r
+ * @note This state is effective in Standby and Shutdown modes only if APC bit\r
+ * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.\r
+ * @note The configuration is lost when exiting the Shutdown mode due to the\r
+ * power-on reset, maintained when exiting the Standby mode.\r
+ * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding\r
+ * PUy bit of PWR_PUCRx register is cleared unless it is reserved.\r
+ * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input\r
+ * parameter at the same time are set.\r
+ * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
+ * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+ * @param GPIONumber: Specify the I/O pins numbers.\r
+ * This parameter can be one of the following values:\r
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+ * I/O pins are available) or the logical OR of several of them to set\r
+ * several bits for a given port in a single API call.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ assert_param(IS_PWR_GPIO(GPIO));\r
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+ switch (GPIO)\r
+ {\r
+ case PWR_GPIO_A:\r
+ SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+ CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));\r
+ break;\r
+ case PWR_GPIO_B:\r
+ SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+ CLEAR_BIT(PWR->PUCRB, GPIONumber);\r
+ break;\r
+ case PWR_GPIO_C:\r
+ SET_BIT(PWR->PDCRC, GPIONumber);\r
+ CLEAR_BIT(PWR->PUCRC, GPIONumber);\r
+ break;\r
+#if defined(GPIOD)\r
+ case PWR_GPIO_D:\r
+ SET_BIT(PWR->PDCRD, GPIONumber);\r
+ CLEAR_BIT(PWR->PUCRD, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOE)\r
+ case PWR_GPIO_E:\r
+ SET_BIT(PWR->PDCRE, GPIONumber);\r
+ CLEAR_BIT(PWR->PUCRE, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOF)\r
+ case PWR_GPIO_F:\r
+ SET_BIT(PWR->PDCRF, GPIONumber);\r
+ CLEAR_BIT(PWR->PUCRF, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOG)\r
+ case PWR_GPIO_G:\r
+ SET_BIT(PWR->PDCRG, GPIONumber);\r
+ CLEAR_BIT(PWR->PUCRG, GPIONumber);\r
+ break;\r
+#endif\r
+ case PWR_GPIO_H:\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+ SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+ SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+ CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+ break;\r
+#if defined(GPIOI)\r
+ case PWR_GPIO_I:\r
+ SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ break;\r
+#endif\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable GPIO pull-down state in Standby and Shutdown modes.\r
+ * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O\r
+ * in pull-down state in Standby and Shutdown modes.\r
+ * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input\r
+ * parameter at the same time are reset.\r
+ * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H\r
+ * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.\r
+ * @param GPIONumber: Specify the I/O pins numbers.\r
+ * This parameter can be one of the following values:\r
+ * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less\r
+ * I/O pins are available) or the logical OR of several of them to reset\r
+ * several bits for a given port in a single API call.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ assert_param(IS_PWR_GPIO(GPIO));\r
+ assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));\r
+\r
+ switch (GPIO)\r
+ {\r
+ case PWR_GPIO_A:\r
+ CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));\r
+ break;\r
+ case PWR_GPIO_B:\r
+ CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));\r
+ break;\r
+ case PWR_GPIO_C:\r
+ CLEAR_BIT(PWR->PDCRC, GPIONumber);\r
+ break;\r
+#if defined(GPIOD)\r
+ case PWR_GPIO_D:\r
+ CLEAR_BIT(PWR->PDCRD, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOE)\r
+ case PWR_GPIO_E:\r
+ CLEAR_BIT(PWR->PDCRE, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOF)\r
+ case PWR_GPIO_F:\r
+ CLEAR_BIT(PWR->PDCRF, GPIONumber);\r
+ break;\r
+#endif\r
+#if defined(GPIOG)\r
+ case PWR_GPIO_G:\r
+ CLEAR_BIT(PWR->PDCRG, GPIONumber);\r
+ break;\r
+#endif\r
+ case PWR_GPIO_H:\r
+#if defined (STM32L496xx) || defined (STM32L4A6xx)\r
+ CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));\r
+#else\r
+ CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));\r
+#endif\r
+ break;\r
+#if defined(GPIOI)\r
+ case PWR_GPIO_I:\r
+ CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));\r
+ break;\r
+#endif\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable pull-up and pull-down configuration.\r
+ * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in\r
+ * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.\r
+ * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding\r
+ * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).\r
+ * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there\r
+ * is no conflict when setting PUy or PDy bit.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnablePullUpPullDownConfig(void)\r
+{\r
+ SET_BIT(PWR->CR3, PWR_CR3_APC);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable pull-up and pull-down configuration.\r
+ * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in\r
+ * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisablePullUpPullDownConfig(void)\r
+{\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_APC);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enable SRAM2 content retention in Standby mode.\r
+ * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in\r
+ * Standby mode and its content is kept.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableSRAM2ContentRetention(void)\r
+{\r
+ SET_BIT(PWR->CR3, PWR_CR3_RRS);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable SRAM2 content retention in Standby mode.\r
+ * @note When RRS bit is reset, SRAM2 is powered off in Standby mode\r
+ * and its content is lost.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableSRAM2ContentRetention(void)\r
+{\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);\r
+}\r
+\r
+\r
+#if defined(PWR_CR3_ENULP)\r
+/**\r
+ * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
+ * @note All the other modes are not affected by this bit.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableBORPVD_ULP(void)\r
+{\r
+ SET_BIT(PWR->CR3, PWR_CR3_ENULP);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.\r
+ * @note All the other modes are not affected by this bit\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableBORPVD_ULP(void)\r
+{\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);\r
+}\r
+#endif /* PWR_CR3_ENULP */\r
+\r
+\r
+#if defined(PWR_CR4_EXT_SMPS_ON)\r
+/**\r
+ * @brief Enable the CFLDO working @ 0.95V.\r
+ * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\r
+ * internal CFLDO can be reduced to 0.95V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableExtSMPS_0V95(void)\r
+{\r
+ SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
+}\r
+\r
+/**\r
+ * @brief Disable the CFLDO working @ 0.95V\r
+ * @note Before SMPS is switched off, the regulated voltage of the\r
+ * internal CFLDO shall be set to 1.00V.\r
+ * 1.00V. is also default operating Range 2 voltage.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableExtSMPS_0V95(void)\r
+{\r
+ CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\r
+}\r
+#endif /* PWR_CR4_EXT_SMPS_ON */\r
+\r
+\r
+#if defined(PWR_CR1_RRSTP)\r
+/**\r
+ * @brief Enable SRAM3 content retention in Stop 2 mode.\r
+ * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in\r
+ * Stop 2 mode and its content is kept.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableSRAM3ContentRetention(void)\r
+{\r
+ SET_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable SRAM3 content retention in Stop 2 mode.\r
+ * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode\r
+ * and its content is lost.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableSRAM3ContentRetention(void)\r
+{\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);\r
+}\r
+#endif /* PWR_CR1_RRSTP */\r
+\r
+#if defined(PWR_CR3_DSIPDEN)\r
+/**\r
+ * @brief Enable pull-down activation on DSI pins.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableDSIPinsPDActivation(void)\r
+{\r
+ SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Disable pull-down activation on DSI pins.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableDSIPinsPDActivation(void)\r
+{\r
+ CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\r
+}\r
+#endif /* PWR_CR3_DSIPDEN */\r
+\r
+#if defined(PWR_CR2_PVME1)\r
+/**\r
+ * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnablePVM1(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_PVM_1);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisablePVM1(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_PVM_1);\r
+}\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+/**\r
+ * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnablePVM2(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_PVM_2);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisablePVM2(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_PVM_2);\r
+}\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+\r
+/**\r
+ * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnablePVM3(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_PVM_3);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisablePVM3(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_PVM_3);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnablePVM4(void)\r
+{\r
+ SET_BIT(PWR->CR2, PWR_PVM_4);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisablePVM4(void)\r
+{\r
+ CLEAR_BIT(PWR->CR2, PWR_PVM_4);\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief Configure the Peripheral Voltage Monitoring (PVM).\r
+ * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the\r
+ * PVM configuration information.\r
+ * @note The API configures a single PVM according to the information contained\r
+ * in the input structure. To configure several PVMs, the API must be singly\r
+ * called for each PVM used.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage thresholds corresponding to each\r
+ * detection level and to each monitored supply.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));\r
+ assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));\r
+\r
+\r
+ /* Configure EXTI 35 to 38 interrupts if so required:\r
+ scan thru PVMType to detect which PVMx is set and\r
+ configure the corresponding EXTI line accordingly. */\r
+ switch (sConfigPVM->PVMType)\r
+ {\r
+#if defined(PWR_CR2_PVME1)\r
+ case PWR_PVM_1:\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVM1_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();\r
+ __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVM1_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+ break;\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+ case PWR_PVM_2:\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVM2_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();\r
+ __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVM2_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+ break;\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+ case PWR_PVM_3:\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVM3_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();\r
+ __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVM3_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+ break;\r
+\r
+ case PWR_PVM_4:\r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVM4_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();\r
+ __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();\r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVM4_EXTI_ENABLE_IT();\r
+ }\r
+\r
+ /* Configure event mode */\r
+ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();\r
+ }\r
+\r
+ /* Configure the edge */\r
+ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+\r
+ if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+ break;\r
+\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enter Low-power Run mode\r
+ * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the\r
+ * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.\r
+ * Additionally, the clock frequency must be reduced below 2 MHz.\r
+ * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must\r
+ * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableLowPowerRunMode(void)\r
+{\r
+ /* Set Regulator parameter */\r
+ SET_BIT(PWR->CR1, PWR_CR1_LPR);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Exit Low-power Run mode.\r
+ * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that\r
+ * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode\r
+ * returns HAL_TIMEOUT status). The system clock frequency can then be\r
+ * increased above 2 MHz.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)\r
+{\r
+ uint32_t wait_loop_index;\r
+\r
+ /* Clear LPR bit */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);\r
+\r
+ /* Wait until REGLPF is reset */\r
+ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;\r
+ while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))\r
+ {\r
+ wait_loop_index--;\r
+ }\r
+ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enter Stop 0 mode.\r
+ * @note In Stop 0 mode, main and low voltage regulators are ON.\r
+ * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.\r
+ * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+ * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+ * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+ * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+ * only to the peripheral requesting it.\r
+ * SRAM1, SRAM2 and register contents are preserved.\r
+ * The BOR is available.\r
+ * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+ * is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+ * @note By keeping the internal regulator ON during Stop 0 mode, the consumption\r
+ * is higher although the startup time is reduced.\r
+ * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction\r
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Stop 0 mode with Main Regulator */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enter Stop 1 mode.\r
+ * @note In Stop 1 mode, only low power voltage regulator is ON.\r
+ * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.\r
+ * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,\r
+ * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability\r
+ * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI\r
+ * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated\r
+ * only to the peripheral requesting it.\r
+ * SRAM1, SRAM2 and register contents are preserved.\r
+ * The BOR is available.\r
+ * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+ * is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+ * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.\r
+ * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction\r
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Stop 1 mode with Low-Power Regulator */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enter Stop 2 mode.\r
+ * @note In Stop 2 mode, only low power voltage regulator is ON.\r
+ * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.\r
+ * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,\r
+ * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability\r
+ * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after\r
+ * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only\r
+ * to the peripheral requesting it.\r
+ * SRAM1, SRAM2 and register contents are preserved.\r
+ * The BOR is available.\r
+ * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.\r
+ * Otherwise, Stop 1 mode is entered.\r
+ * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,\r
+ * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register\r
+ * is set; the MSI oscillator is selected if STOPWUCK is cleared.\r
+ * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction\r
+ * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Set Stop mode 2 */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+}\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief Enter Shutdown mode.\r
+ * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched\r
+ * off. The voltage regulator is disabled and Vcore domain is powered off.\r
+ * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.\r
+ * The BOR is not available.\r
+ * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnterSHUTDOWNMode(void)\r
+{\r
+\r
+ /* Set Shutdown mode */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD/PVMx interrupt request.\r
+ * @note This API should be called under the PVD_PVM_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_PVD_PVM_IRQHandler(void)\r
+{\r
+ /* Check PWR exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+\r
+ /* Clear PVD exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+ /* Next, successively check PVMx exti flags */\r
+#if defined(PWR_CR2_PVME1)\r
+ if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)\r
+ {\r
+ /* PWR PVM1 interrupt user callback */\r
+ HAL_PWREx_PVM1Callback();\r
+\r
+ /* Clear PVM1 exti pending bit */\r
+ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();\r
+ }\r
+#endif /* PWR_CR2_PVME1 */\r
+#if defined(PWR_CR2_PVME2)\r
+ if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)\r
+ {\r
+ /* PWR PVM2 interrupt user callback */\r
+ HAL_PWREx_PVM2Callback();\r
+\r
+ /* Clear PVM2 exti pending bit */\r
+ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();\r
+ }\r
+#endif /* PWR_CR2_PVME2 */\r
+ if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)\r
+ {\r
+ /* PWR PVM3 interrupt user callback */\r
+ HAL_PWREx_PVM3Callback();\r
+\r
+ /* Clear PVM3 exti pending bit */\r
+ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();\r
+ }\r
+ if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)\r
+ {\r
+ /* PWR PVM4 interrupt user callback */\r
+ HAL_PWREx_PVM4Callback();\r
+\r
+ /* Clear PVM4 exti pending bit */\r
+ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+\r
+#if defined(PWR_CR2_PVME1)\r
+/**\r
+ * @brief PWR PVM1 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_PVM1Callback(void)\r
+{\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ HAL_PWREx_PVM1Callback() API can be implemented in the user file\r
+ */\r
+}\r
+#endif /* PWR_CR2_PVME1 */\r
+\r
+#if defined(PWR_CR2_PVME2)\r
+/**\r
+ * @brief PWR PVM2 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_PVM2Callback(void)\r
+{\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ HAL_PWREx_PVM2Callback() API can be implemented in the user file\r
+ */\r
+}\r
+#endif /* PWR_CR2_PVME2 */\r
+\r
+/**\r
+ * @brief PWR PVM3 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_PVM3Callback(void)\r
+{\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ HAL_PWREx_PVM3Callback() API can be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWR PVM4 interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWREx_PVM4Callback(void)\r
+{\r
+ /* NOTE : This function should not be modified; when the callback is needed,\r
+ HAL_PWREx_PVM4Callback() API can be implemented in the user file\r
+ */\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff