--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32l4xx_ll_usb.c\r
+ * @author MCD Application Team\r
+ * @brief USB Low Layer HAL module driver.\r
+ *\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the USB Peripheral Controller:\r
+ * + Initialization/de-initialization functions\r
+ * + I/O operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r
+\r
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r
+\r
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l4xx_hal.h"\r
+\r
+/** @addtogroup STM32L4xx_LL_USB_DRIVER\r
+ * @{\r
+ */\r
+\r
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r
+#if defined (USB) || defined (USB_OTG_FS)\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+#if defined (USB_OTG_FS)\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization/de-initialization functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the USB Core\r
+ * @param USBx USB Instance\r
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ HAL_StatusTypeDef ret;\r
+\r
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r
+ {\r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+\r
+ /* Init The ULPI Interface */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r
+\r
+ /* Select vbus source */\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r
+ if (cfg.use_external_vbus == 1U)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r
+ }\r
+ /* Reset after a PHY select */\r
+ ret = USB_CoreReset(USBx);\r
+ }\r
+ else /* FS interface (embedded Phy) */\r
+ {\r
+ /* Select FS Embedded PHY */\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r
+\r
+ /* Reset after a PHY select and set Host mode */\r
+ ret = USB_CoreReset(USBx);\r
+\r
+ if (cfg.battery_charging_enable == 0U)\r
+ {\r
+ /* Activate the USB Transceiver */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\r
+ }\r
+ else\r
+ {\r
+ /* Deactivate the USB Transceiver */\r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r
+ }\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set the USB turnaround time\r
+ * @param USBx USB Instance\r
+ * @param hclk: AHB clock frequency\r
+ * @retval USB turnaround time In PHY Clocks number\r
+ */\r
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,\r
+ uint32_t hclk, uint8_t speed)\r
+{\r
+ uint32_t UsbTrd;\r
+\r
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency\r
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response\r
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access\r
+ latency to the Data FIFO */\r
+ if (speed == USBD_FS_SPEED)\r
+ {\r
+ if ((hclk >= 14200000U) && (hclk < 15000000U))\r
+ {\r
+ /* hclk Clock Range between 14.2-15 MHz */\r
+ UsbTrd = 0xFU;\r
+ }\r
+ else if ((hclk >= 15000000U) && (hclk < 16000000U))\r
+ {\r
+ /* hclk Clock Range between 15-16 MHz */\r
+ UsbTrd = 0xEU;\r
+ }\r
+ else if ((hclk >= 16000000U) && (hclk < 17200000U))\r
+ {\r
+ /* hclk Clock Range between 16-17.2 MHz */\r
+ UsbTrd = 0xDU;\r
+ }\r
+ else if ((hclk >= 17200000U) && (hclk < 18500000U))\r
+ {\r
+ /* hclk Clock Range between 17.2-18.5 MHz */\r
+ UsbTrd = 0xCU;\r
+ }\r
+ else if ((hclk >= 18500000U) && (hclk < 20000000U))\r
+ {\r
+ /* hclk Clock Range between 18.5-20 MHz */\r
+ UsbTrd = 0xBU;\r
+ }\r
+ else if ((hclk >= 20000000U) && (hclk < 21800000U))\r
+ {\r
+ /* hclk Clock Range between 20-21.8 MHz */\r
+ UsbTrd = 0xAU;\r
+ }\r
+ else if ((hclk >= 21800000U) && (hclk < 24000000U))\r
+ {\r
+ /* hclk Clock Range between 21.8-24 MHz */\r
+ UsbTrd = 0x9U;\r
+ }\r
+ else if ((hclk >= 24000000U) && (hclk < 27700000U))\r
+ {\r
+ /* hclk Clock Range between 24-27.7 MHz */\r
+ UsbTrd = 0x8U;\r
+ }\r
+ else if ((hclk >= 27700000U) && (hclk < 32000000U))\r
+ {\r
+ /* hclk Clock Range between 27.7-32 MHz */\r
+ UsbTrd = 0x7U;\r
+ }\r
+ else /* if(hclk >= 32000000) */\r
+ {\r
+ /* hclk Clock Range between 32-200 MHz */\r
+ UsbTrd = 0x6U;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ UsbTrd = USBD_DEFAULT_TRDT_VALUE;\r
+ }\r
+\r
+ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r
+ USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EnableGlobalInt\r
+ * Enables the controller's Global Int in the AHB Config reg\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DisableGlobalInt\r
+ * Disable the controller's Global Int in the AHB Config reg\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetCurrentMode : Set functional mode\r
+ * @param USBx Selected device\r
+ * @param mode current core mode\r
+ * This parameter can be one of these values:\r
+ * @arg USB_DEVICE_MODE: Peripheral mode\r
+ * @arg USB_HOST_MODE: Host mode\r
+ * @arg USB_DRD_MODE: Dual Role Device mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)\r
+{\r
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\r
+\r
+ if (mode == USB_HOST_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;\r
+ }\r
+ else if (mode == USB_DEVICE_MODE)\r
+ {\r
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ HAL_Delay(50U);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers\r
+ * for device mode\r
+ * @param USBx Selected device\r
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t i;\r
+\r
+ for (i = 0U; i < 15U; i++)\r
+ {\r
+ USBx->DIEPTXF[i] = 0U;\r
+ }\r
+\r
+ /* VBUS Sensing setup */\r
+ if (cfg.vbus_sensing_enable == 0U)\r
+ {\r
+ /* Deactivate VBUS Sensing B */\r
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;\r
+\r
+ /* B-peripheral session valid override enable */\r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r
+ USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r
+ }\r
+ else\r
+ {\r
+ /* Enable HW VBUS sensing */\r
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r
+ }\r
+\r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0U;\r
+\r
+ /* Device mode configuration */\r
+ USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r
+\r
+ /* Set Core speed to Full speed mode */\r
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);\r
+\r
+ /* Flush the FIFOs */\r
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+\r
+ if (USB_FlushRxFifo(USBx) != HAL_OK)\r
+ {\r
+ ret = HAL_ERROR;\r
+ }\r
+\r
+ /* Clear all pending Device Interrupts */\r
+ USBx_DEVICE->DIEPMSK = 0U;\r
+ USBx_DEVICE->DOEPMSK = 0U;\r
+ USBx_DEVICE->DAINTMSK = 0U;\r
+\r
+ for (i = 0U; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r
+ {\r
+ if (i == 0U)\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(i)->DIEPCTL = 0U;\r
+ }\r
+\r
+ USBx_INEP(i)->DIEPTSIZ = 0U;\r
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
+ }\r
+\r
+ for (i = 0U; i < cfg.dev_endpoints; i++)\r
+ {\r
+ if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+ {\r
+ if (i == 0U)\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(i)->DOEPCTL = 0U;\r
+ }\r
+\r
+ USBx_OUTEP(i)->DOEPTSIZ = 0U;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
+ }\r
+\r
+ USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r
+\r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0U;\r
+\r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xBFFFFFFFU;\r
+\r
+ /* Enable the common interrupts */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
+\r
+ /* Enable interrupts matching to the Device mode ONLY */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\r
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\r
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;\r
+\r
+ if (cfg.Sof_enable != 0U)\r
+ {\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r
+ }\r
+\r
+ if (cfg.vbus_sensing_enable == 1U)\r
+ {\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO\r
+ * @param USBx Selected device\r
+ * @param num FIFO number\r
+ * This parameter can be a value from 1 to 15\r
+ 15 means Flush all Tx FIFOs\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)\r
+{\r
+ uint32_t count = 0U;\r
+\r
+ USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));\r
+\r
+ do\r
+ {\r
+ if (++count > 200000U)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_FlushRxFifo : Flush Rx FIFO\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0;\r
+\r
+ USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r
+\r
+ do\r
+ {\r
+ if (++count > 200000U)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register\r
+ * depending the PHY type and the enumeration speed of the device.\r
+ * @param USBx Selected device\r
+ * @param speed device speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @retval Hal status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ USBx_DEVICE->DCFG |= speed;\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_GetDevSpeed Return the Dev Speed\r
+ * @param USBx Selected device\r
+ * @retval speed device speed\r
+ * This parameter can be one of these values:\r
+ * @arg PCD_SPEED_FULL: Full speed mode\r
+ */\r
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint8_t speed;\r
+ uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;\r
+\r
+ if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||\r
+ (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))\r
+ {\r
+ speed = USBD_FS_SPEED;\r
+ }\r
+ else\r
+ {\r
+ speed = 0xFU;\r
+ }\r
+\r
+ return speed;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure an endpoint\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ if (ep->is_in == 1U)\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
+\r
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
+ ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+ USB_OTG_DIEPCTL_USBAEP;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
+\r
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
+ ((uint32_t)ep->type << 18) |\r
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+ USB_OTG_DOEPCTL_USBAEP;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure a dedicated endpoint\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r
+ ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+ USB_OTG_DIEPCTL_USBAEP;\r
+ }\r
+\r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r
+ ((uint32_t)ep->type << 18) | (epnum << 22) |\r
+ USB_OTG_DOEPCTL_USBAEP;\r
+ }\r
+\r
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize an endpoint\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |\r
+ USB_OTG_DIEPCTL_MPSIZ |\r
+ USB_OTG_DIEPCTL_TXFNUM |\r
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r
+ USB_OTG_DIEPCTL_EPTYP);\r
+ }\r
+ else\r
+ {\r
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |\r
+ USB_OTG_DOEPCTL_MPSIZ |\r
+ USB_OTG_DOEPCTL_SD0PID_SEVNFRM |\r
+ USB_OTG_DOEPCTL_EPTYP);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize a dedicated endpoint\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ /* Read DEPCTLn register */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;\r
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+ uint16_t pktcnt;\r
+\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
+\r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));\r
+ }\r
+ }\r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0U)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+\r
+ (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len);\r
+ }\r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */\r
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
+\r
+ if (ep->xfer_len == 0U)\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+ }\r
+ else\r
+ {\r
+ pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);\r
+ }\r
+\r
+ if (ep->type == EP_TYPE_ISOC)\r
+ {\r
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r
+ }\r
+ }\r
+ /* EP enable */\r
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ /* Zero Length Packet? */\r
+ if (ep->xfer_len == 0U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ }\r
+ else\r
+ {\r
+ /* Program the transfer size and packet count\r
+ * as follows: xfersize = N * maxpacket +\r
+ * short_packet pktcnt = N + (short_packet\r
+ * exist ? 1 : 0)\r
+ */\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r
+\r
+ if (ep->xfer_len > ep->maxpacket)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r
+ }\r
+\r
+ /* EP enable, IN data in FIFO */\r
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r
+\r
+ /* Enable the Tx FIFO Empty Interrupt for this EP */\r
+ if (ep->xfer_len > 0U)\r
+ {\r
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\r
+ }\r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Program the transfer size and packet count as follows:\r
+ * pktcnt = N\r
+ * xfersize = N * maxpacket\r
+ */\r
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r
+\r
+ if (ep->xfer_len > 0U)\r
+ {\r
+ ep->xfer_len = ep->maxpacket;\r
+ }\r
+\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));\r
+\r
+ /* EP enable */\r
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated\r
+ * with the EP/channel\r
+ * @param USBx Selected device\r
+ * @param src pointer to source buffer\r
+ * @param ch_ep_num endpoint or host channel number\r
+ * @param len Number of bytes to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t *pSrc = (uint32_t *)src;\r
+ uint32_t count32b, i;\r
+\r
+ count32b = ((uint32_t)len + 3U) / 4U;\r
+ for (i = 0U; i < count32b; i++)\r
+ {\r
+ USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);\r
+ pSrc++;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadPacket : read a packet from the RX FIFO\r
+ * @param USBx Selected device\r
+ * @param dest source pointer\r
+ * @param len Number of bytes to read\r
+ * @retval pointer to destination buffer\r
+ */\r
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t *pDest = (uint32_t *)dest;\r
+ uint32_t i;\r
+ uint32_t count32b = ((uint32_t)len + 3U) / 4U;\r
+\r
+ for (i = 0U; i < count32b; i++)\r
+ {\r
+ __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));\r
+ pDest++;\r
+ }\r
+\r
+ return ((void *)pDest);\r
+}\r
+\r
+/**\r
+ * @brief USB_EPSetStall : set a stall condition over an EP\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ if (ep->is_in == 1U)\r
+ {\r
+ if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);\r
+ }\r
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r
+ }\r
+ else\r
+ {\r
+ if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);\r
+ }\r
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPClearStall : Clear a stall condition over an EP\r
+ * @param USBx Selected device\r
+ * @param ep pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t epnum = (uint32_t)ep->num;\r
+\r
+ if (ep->is_in == 1U)\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
+ {\r
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r
+ {\r
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_StopDevice : Stop the usb device mode\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ HAL_StatusTypeDef ret;\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t i;\r
+\r
+ /* Clear Pending interrupt */\r
+ for (i = 0U; i < 15U; i++)\r
+ {\r
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;\r
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r
+ }\r
+\r
+ /* Clear interrupt masks */\r
+ USBx_DEVICE->DIEPMSK = 0U;\r
+ USBx_DEVICE->DOEPMSK = 0U;\r
+ USBx_DEVICE->DAINTMSK = 0U;\r
+\r
+ /* Flush the FIFO */\r
+ ret = USB_FlushRxFifo(USBx);\r
+ if (ret != HAL_OK)\r
+ {\r
+ return ret;\r
+ }\r
+\r
+ ret = USB_FlushTxFifo(USBx, 0x10U);\r
+ if (ret != HAL_OK)\r
+ {\r
+ return ret;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevAddress : Stop the usb device mode\r
+ * @param USBx Selected device\r
+ * @param address new device address to be assigned\r
+ * This parameter can be a value from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);\r
+ USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;\r
+ HAL_Delay(3U);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\r
+ HAL_Delay(3U);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadInterrupts: return the global USB interrupt status\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ tmpreg = USBx->GINTSTS;\r
+ tmpreg &= USBx->GINTMSK;\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t tmpreg;\r
+\r
+ tmpreg = USBx_DEVICE->DAINT;\r
+ tmpreg &= USBx_DEVICE->DAINTMSK;\r
+\r
+ return ((tmpreg & 0xffff0000U) >> 16);\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t tmpreg;\r
+\r
+ tmpreg = USBx_DEVICE->DAINT;\r
+ tmpreg &= USBx_DEVICE->DAINTMSK;\r
+\r
+ return ((tmpreg & 0xFFFFU));\r
+}\r
+\r
+/**\r
+ * @brief Returns Device OUT EP Interrupt register\r
+ * @param USBx Selected device\r
+ * @param epnum endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device OUT EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t tmpreg;\r
+\r
+ tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;\r
+ tmpreg &= USBx_DEVICE->DOEPMSK;\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns Device IN EP Interrupt register\r
+ * @param USBx Selected device\r
+ * @param epnum endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device IN EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t tmpreg, msk, emp;\r
+\r
+ msk = USBx_DEVICE->DIEPMSK;\r
+ emp = USBx_DEVICE->DIEPEMPMSK;\r
+ msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;\r
+ tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief USB_ClearInterrupts: clear a USB interrupt\r
+ * @param USBx Selected device\r
+ * @param interrupt interrupt flag\r
+ * @retval None\r
+ */\r
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r
+{\r
+ USBx->GINTSTS |= interrupt;\r
+}\r
+\r
+/**\r
+ * @brief Returns USB core mode\r
+ * @param USBx Selected device\r
+ * @retval return core mode : Host or Device\r
+ * This parameter can be one of these values:\r
+ * 0 : Host\r
+ * 1 : Device\r
+ */\r
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ return ((USBx->GINTSTS) & 0x1U);\r
+}\r
+\r
+/**\r
+ * @brief Activate EP0 for Setup transactions\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ /* Set the MPS of the IN EP based on the enumeration speed */\r
+ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r
+\r
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r
+ {\r
+ USBx_INEP(0U)->DIEPCTL |= 3U;\r
+ }\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Prepare the EP0 to start the first control setup\r
+ * @param USBx Selected device\r
+ * @param psetup pointer to setup packet\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)\r
+{\r
+ UNUSED(psetup);\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\r
+\r
+ if (gSNPSiD > USB_OTG_CORE_ID_300A)\r
+ {\r
+ if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ }\r
+\r
+ USBx_OUTEP(0U)->DOEPTSIZ = 0U;\r
+ USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r
+ USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);\r
+ USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Reset the USB Core (needed after USB clock settings change)\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t count = 0U;\r
+\r
+ /* Wait for AHB master IDLE state. */\r
+ do\r
+ {\r
+ if (++count > 200000U)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);\r
+\r
+ /* Core Soft Reset */\r
+ count = 0U;\r
+ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r
+\r
+ do\r
+ {\r
+ if (++count > 200000U)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_HostInit : Initializes the USB OTG controller registers\r
+ * for Host mode\r
+ * @param USBx Selected device\r
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t i;\r
+\r
+ /* Restart the Phy Clock */\r
+ USBx_PCGCCTL = 0U;\r
+\r
+ /* Disable VBUS sensing */\r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\r
+\r
+ /* Disable Battery chargin detector */\r
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\r
+\r
+ /* Set default Max speed support */\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\r
+\r
+ /* Make sure the FIFOs are flushed. */\r
+ (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\r
+ (void)USB_FlushRxFifo(USBx);\r
+\r
+ /* Clear all pending HC Interrupts */\r
+ for (i = 0U; i < cfg.Host_channels; i++)\r
+ {\r
+ USBx_HC(i)->HCINT = 0xFFFFFFFFU;\r
+ USBx_HC(i)->HCINTMSK = 0U;\r
+ }\r
+\r
+ /* Enable VBUS driving */\r
+ (void)USB_DriveVbus(USBx, 1U);\r
+\r
+ HAL_Delay(200U);\r
+\r
+ /* Disable all interrupts. */\r
+ USBx->GINTMSK = 0U;\r
+\r
+ /* Clear any pending interrupts */\r
+ USBx->GINTSTS = 0xFFFFFFFFU;\r
+\r
+ /* set Rx FIFO size */\r
+ USBx->GRXFSIZ = 0x80U;\r
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);\r
+ USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);\r
+ /* Enable the common interrupts */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r
+\r
+ /* Enable interrupts matching to the Host mode ONLY */\r
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \\r
+ USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \\r
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the\r
+ * HCFG register on the PHY type and set the right frame interval\r
+ * @param USBx Selected device\r
+ * @param freq clock frequency\r
+ * This parameter can be one of these values:\r
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock\r
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r
+ USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;\r
+\r
+ if (freq == HCFG_48_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = 48000U;\r
+ }\r
+ else if (freq == HCFG_6_MHZ)\r
+ {\r
+ USBx_HOST->HFIR = 6000U;\r
+ }\r
+ else\r
+ {\r
+ /* ... */\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+* @brief USB_OTG_ResetPort : Reset Host Port\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ * @note (1)The application must wait at least 10 ms\r
+ * before clearing the reset bit.\r
+ */\r
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ __IO uint32_t hprt0 = 0U;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+\r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
+\r
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);\r
+ HAL_Delay(100U); /* See Note #1 */\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);\r
+ HAL_Delay(10U);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DriveVbus : activate or de-activate vbus\r
+ * @param state VBUS state\r
+ * This parameter can be one of these values:\r
+ * 0 : VBUS Active\r
+ * 1 : VBUS Inactive\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ __IO uint32_t hprt0 = 0U;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+\r
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r
+\r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))\r
+ {\r
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);\r
+ }\r
+ if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))\r
+ {\r
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Return Host Core speed\r
+ * @param USBx Selected device\r
+ * @retval speed : Host speed\r
+ * This parameter can be one of these values:\r
+ * @arg HCD_SPEED_FULL: Full speed mode\r
+ * @arg HCD_SPEED_LOW: Low speed mode\r
+ */\r
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ __IO uint32_t hprt0 = 0U;\r
+\r
+ hprt0 = USBx_HPRT0;\r
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r
+}\r
+\r
+/**\r
+ * @brief Return Host Current Frame number\r
+ * @param USBx Selected device\r
+ * @retval current frame number\r
+*/\r
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r
+}\r
+\r
+/**\r
+ * @brief Initialize a host channel\r
+ * @param USBx Selected device\r
+ * @param ch_num Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param epnum Endpoint number\r
+ * This parameter can be a value from 1 to 15\r
+ * @param dev_address Current device address\r
+ * This parameter can be a value from 0 to 255\r
+ * @param speed Current device speed\r
+ * This parameter can be one of these values:\r
+ * @arg USB_OTG_SPEED_FULL: Full speed mode\r
+ * @arg USB_OTG_SPEED_LOW: Low speed mode\r
+ * @param ep_type Endpoint Type\r
+ * This parameter can be one of these values:\r
+ * @arg EP_TYPE_CTRL: Control type\r
+ * @arg EP_TYPE_ISOC: Isochronous type\r
+ * @arg EP_TYPE_BULK: Bulk type\r
+ * @arg EP_TYPE_INTR: Interrupt type\r
+ * @param mps Max Packet Size\r
+ * This parameter can be a value from 0 to32K\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r
+ uint8_t ch_num,\r
+ uint8_t epnum,\r
+ uint8_t dev_address,\r
+ uint8_t speed,\r
+ uint8_t ep_type,\r
+ uint16_t mps)\r
+{\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t HCcharEpDir, HCcharLowSpeed;\r
+\r
+ /* Clear old interrupt conditions for this host channel. */\r
+ USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;\r
+\r
+ /* Enable channel interrupts required for this transfer. */\r
+ switch (ep_type)\r
+ {\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\r
+ USB_OTG_HCINTMSK_STALLM |\r
+ USB_OTG_HCINTMSK_TXERRM |\r
+ USB_OTG_HCINTMSK_DTERRM |\r
+ USB_OTG_HCINTMSK_AHBERR |\r
+ USB_OTG_HCINTMSK_NAKM;\r
+\r
+ if ((epnum & 0x80U) == 0x80U)\r
+ {\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ }\r
+ break;\r
+\r
+ case EP_TYPE_INTR:\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\r
+ USB_OTG_HCINTMSK_STALLM |\r
+ USB_OTG_HCINTMSK_TXERRM |\r
+ USB_OTG_HCINTMSK_DTERRM |\r
+ USB_OTG_HCINTMSK_NAKM |\r
+ USB_OTG_HCINTMSK_AHBERR |\r
+ USB_OTG_HCINTMSK_FRMORM;\r
+\r
+ if ((epnum & 0x80U) == 0x80U)\r
+ {\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r
+ }\r
+\r
+ break;\r
+\r
+ case EP_TYPE_ISOC:\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\r
+ USB_OTG_HCINTMSK_ACKM |\r
+ USB_OTG_HCINTMSK_AHBERR |\r
+ USB_OTG_HCINTMSK_FRMORM;\r
+\r
+ if ((epnum & 0x80U) == 0x80U)\r
+ {\r
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);\r
+ }\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ /* Enable the top level host channel interrupt. */\r
+ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);\r
+\r
+ /* Make sure host channel interrupts are enabled. */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r
+\r
+ /* Program the HCCHAR register */\r
+ if ((epnum & 0x80U) == 0x80U)\r
+ {\r
+ HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;\r
+ }\r
+ else\r
+ {\r
+ HCcharEpDir = 0U;\r
+ }\r
+\r
+ if (speed == HPRT0_PRTSPD_LOW_SPEED)\r
+ {\r
+ HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;\r
+ }\r
+ else\r
+ {\r
+ HCcharLowSpeed = 0U;\r
+ }\r
+\r
+ USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |\r
+ ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |\r
+ (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |\r
+ ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;\r
+\r
+ if (ep_type == EP_TYPE_INTR)\r
+ {\r
+ USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief Start a transfer over a host channel\r
+ * @param USBx Selected device\r
+ * @param hc pointer to host channel structure\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t ch_num = (uint32_t)hc->ch_num;\r
+ static __IO uint32_t tmpreg = 0U;\r
+ uint8_t is_oddframe;\r
+ uint16_t len_words;\r
+ uint16_t num_packets;\r
+ uint16_t max_hc_pkt_count = 256U;\r
+\r
+ /* Compute the expected number of packets associated to the transfer */\r
+ if (hc->xfer_len > 0U)\r
+ {\r
+ num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);\r
+\r
+ if (num_packets > max_hc_pkt_count)\r
+ {\r
+ num_packets = max_hc_pkt_count;\r
+ hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ num_packets = 1U;\r
+ }\r
+ if (hc->ep_is_in != 0U)\r
+ {\r
+ hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r
+ }\r
+\r
+ /* Initialize the HCTSIZn register */\r
+ USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |\r
+ (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
+ (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);\r
+\r
+ is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;\r
+ USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r
+ USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;\r
+\r
+ /* Set host channel enable */\r
+ tmpreg = USBx_HC(ch_num)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+\r
+ /* make sure to set the correct ep direction */\r
+ if (hc->ep_is_in != 0U)\r
+ {\r
+ tmpreg |= USB_OTG_HCCHAR_EPDIR;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~USB_OTG_HCCHAR_EPDIR;\r
+ }\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(ch_num)->HCCHAR = tmpreg;\r
+\r
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))\r
+ {\r
+ switch (hc->ep_type)\r
+ {\r
+ /* Non periodic transfer */\r
+ case EP_TYPE_CTRL:\r
+ case EP_TYPE_BULK:\r
+\r
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
+\r
+ /* check if there is enough space in FIFO space */\r
+ if (len_words > (USBx->HNPTXSTS & 0xFFFFU))\r
+ {\r
+ /* need to process data in nptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r
+ }\r
+ break;\r
+\r
+ /* Periodic transfer */\r
+ case EP_TYPE_INTR:\r
+ case EP_TYPE_ISOC:\r
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r
+ /* check if there is enough space in FIFO space */\r
+ if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */\r
+ {\r
+ /* need to process data in ptxfempty interrupt */\r
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Write packet into the Tx FIFO. */\r
+ (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read all host channel interrupts status\r
+ * @param USBx Selected device\r
+ * @retval HAL state\r
+ */\r
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ return ((USBx_HOST->HAINT) & 0xFFFFU);\r
+}\r
+\r
+/**\r
+ * @brief Halt a host channel\r
+ * @param USBx Selected device\r
+ * @param hc_num Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t hcnum = (uint32_t)hc_num;\r
+ uint32_t count = 0U;\r
+ uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;\r
+\r
+ /* Check for space in the request queue to issue the halt. */\r
+ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+\r
+ if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do\r
+ {\r
+ if (++count > 1000U)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r
+\r
+ if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r
+ do\r
+ {\r
+ if (++count > 1000U)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+ else\r
+ {\r
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initiate Do Ping protocol\r
+ * @param USBx Selected device\r
+ * @param hc_num Host Channel number\r
+ * This parameter can be a value from 1 to 15\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t chnum = (uint32_t)ch_num;\r
+ uint32_t num_packets = 1U;\r
+ uint32_t tmpreg;\r
+\r
+ USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r
+ USB_OTG_HCTSIZ_DOPING;\r
+\r
+ /* Set host channel enable */\r
+ tmpreg = USBx_HC(chnum)->HCCHAR;\r
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r
+ tmpreg |= USB_OTG_HCCHAR_CHENA;\r
+ USBx_HC(chnum)->HCCHAR = tmpreg;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Host Core\r
+ * @param USBx Selected device\r
+ * @retval HAL state\r
+ */\r
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+ uint32_t count = 0U;\r
+ uint32_t value;\r
+ uint32_t i;\r
+\r
+\r
+ (void)USB_DisableGlobalInt(USBx);\r
+\r
+ /* Flush FIFO */\r
+ (void)USB_FlushTxFifo(USBx, 0x10U);\r
+ (void)USB_FlushRxFifo(USBx);\r
+\r
+ /* Flush out any leftover queued requests. */\r
+ for (i = 0U; i <= 15U; i++)\r
+ {\r
+ value = USBx_HC(i)->HCCHAR;\r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value &= ~USB_OTG_HCCHAR_CHENA;\r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ USBx_HC(i)->HCCHAR = value;\r
+ }\r
+\r
+ /* Halt all channels to put them into a known state. */\r
+ for (i = 0U; i <= 15U; i++)\r
+ {\r
+ value = USBx_HC(i)->HCCHAR;\r
+ value |= USB_OTG_HCCHAR_CHDIS;\r
+ value |= USB_OTG_HCCHAR_CHENA;\r
+ value &= ~USB_OTG_HCCHAR_EPDIR;\r
+ USBx_HC(i)->HCCHAR = value;\r
+\r
+ do\r
+ {\r
+ if (++count > 1000U)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r
+ }\r
+\r
+ /* Clear any pending Host interrupts */\r
+ USBx_HOST->HAINT = 0xFFFFFFFFU;\r
+ USBx->GINTSTS = 0xFFFFFFFFU;\r
+ (void)USB_EnableGlobalInt(USBx);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ActivateRemoteWakeup active remote wakeup signalling\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r
+ {\r
+ /* active Remote wakeup signalling */\r
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r
+{\r
+ uint32_t USBx_BASE = (uint32_t)USBx;\r
+\r
+ /* active Remote wakeup signalling */\r
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r
+\r
+ return HAL_OK;\r
+}\r
+#endif /* defined (USB_OTG_FS) */\r
+\r
+#if defined (USB)\r
+/**\r
+ * @brief Initializes the USB Core\r
+ * @param USBx: USB Instance\r
+ * @param cfg : pointer to a USB_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(cfg);\r
+\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EnableGlobalInt\r
+ * Enables the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)\r
+{\r
+ uint16_t winterruptmask;\r
+\r
+ /* Set winterruptmask variable */\r
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |\r
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
+\r
+ /* Set interrupt mask */\r
+ USBx->CNTR |= winterruptmask;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DisableGlobalInt\r
+ * Disable the controller's Global Int in the AHB Config reg\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+*/\r
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)\r
+{\r
+ uint16_t winterruptmask;\r
+\r
+ /* Set winterruptmask variable */\r
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |\r
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |\r
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |\r
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;\r
+\r
+ /* Clear interrupt mask */\r
+ USBx->CNTR &= ~winterruptmask;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetCurrentMode : Set functional mode\r
+ * @param USBx : Selected device\r
+ * @param mode : current core mode\r
+ * This parameter can be one of the these values:\r
+ * @arg USB_DEVICE_MODE: Peripheral mode mode\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(mode);\r
+\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevInit : Initializes the USB controller registers\r
+ * for device mode\r
+ * @param USBx : Selected device\r
+ * @param cfg : pointer to a USB_CfgTypeDef structure that contains\r
+ * the configuration information for the specified USBx peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(cfg);\r
+\r
+ /* Init Device */\r
+ /*CNTR_FRES = 1*/\r
+ USBx->CNTR = USB_CNTR_FRES;\r
+\r
+ /*CNTR_FRES = 0*/\r
+ USBx->CNTR = 0;\r
+\r
+ /*Clear pending interrupts*/\r
+ USBx->ISTR = 0;\r
+\r
+ /*Set Btable Address*/\r
+ USBx->BTABLE = BTABLE_ADDRESS;\r
+\r
+ /* Enable USB Device Interrupt mask */\r
+ (void)USB_EnableGlobalInt(USBx);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevSpeed :Initializes the device speed\r
+ * depending on the PHY type and the enumeration speed of the device.\r
+ * @param USBx Selected device\r
+ * @param speed device speed\r
+ * @retval Hal status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(speed);\r
+\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO\r
+ * @param USBx : Selected device\r
+ * @param num : FIFO number\r
+ * This parameter can be a value from 1 to 15\r
+ 15 means Flush all Tx FIFOs\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(num);\r
+\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_FlushRxFifo : Flush Rx FIFO\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Activate and configure an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+ HAL_StatusTypeDef ret = HAL_OK;\r
+ uint16_t wEpRegVal;\r
+\r
+ wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;\r
+\r
+ /* initialize Endpoint */\r
+ switch (ep->type)\r
+ {\r
+ case EP_TYPE_CTRL:\r
+ wEpRegVal |= USB_EP_CONTROL;\r
+ break;\r
+\r
+ case EP_TYPE_BULK:\r
+ wEpRegVal |= USB_EP_BULK;\r
+ break;\r
+\r
+ case EP_TYPE_INTR:\r
+ wEpRegVal |= USB_EP_INTERRUPT;\r
+ break;\r
+\r
+ case EP_TYPE_ISOC:\r
+ wEpRegVal |= USB_EP_ISOCHRONOUS;\r
+ break;\r
+\r
+ default:\r
+ ret = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);\r
+\r
+ PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);\r
+\r
+ if (ep->doublebuffer == 0U)\r
+ {\r
+ if (ep->is_in != 0U)\r
+ {\r
+ /*Set the endpoint Transmit buffer address */\r
+ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Configure NAK status for the Endpoint */\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+ }\r
+ else\r
+ {\r
+ /* Configure TX Endpoint to disabled state */\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*Set the endpoint Receive buffer address */\r
+ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);\r
+ /*Set the endpoint Receive buffer counter*/\r
+ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ /* Configure VALID status for the Endpoint*/\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+ }\r
+ }\r
+ /*Double Buffer*/\r
+ else\r
+ {\r
+ /* Set the endpoint as double buffered */\r
+ PCD_SET_EP_DBUF(USBx, ep->num);\r
+ /* Set buffer address for double buffered mode */\r
+ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);\r
+\r
+ if (ep->is_in == 0U)\r
+ {\r
+ /* Clear the data toggle bits for the endpoint IN/OUT */\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+ /* Reset value of the data toggle bits for the endpoint out */\r
+ PCD_TX_DTOG(USBx, ep->num);\r
+\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ }\r
+ else\r
+ {\r
+ /* Clear the data toggle bits for the endpoint IN/OUT */\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+ PCD_RX_DTOG(USBx, ep->num);\r
+\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Configure NAK status for the Endpoint */\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+ }\r
+ else\r
+ {\r
+ /* Configure TX Endpoint to disabled state */\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ }\r
+\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+ }\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/**\r
+ * @brief De-activate and de-initialize an endpoint\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+ if (ep->doublebuffer == 0U)\r
+ {\r
+ if (ep->is_in != 0U)\r
+ {\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+ /* Configure DISABLE status for the Endpoint*/\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ }\r
+ else\r
+ {\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ /* Configure DISABLE status for the Endpoint*/\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+ }\r
+ }\r
+ /*Double Buffer*/\r
+ else\r
+ {\r
+ if (ep->is_in == 0U)\r
+ {\r
+ /* Clear the data toggle bits for the endpoint IN/OUT*/\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+ /* Reset value of the data toggle bits for the endpoint out*/\r
+ PCD_TX_DTOG(USBx, ep->num);\r
+\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ }\r
+ else\r
+ {\r
+ /* Clear the data toggle bits for the endpoint IN/OUT*/\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+ PCD_RX_DTOG(USBx, ep->num);\r
+ /* Configure DISABLE status for the Endpoint*/\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+ uint16_t pmabuffer;\r
+ uint32_t len;\r
+\r
+ /* IN endpoint */\r
+ if (ep->is_in == 1U)\r
+ {\r
+ /*Multi packet transfer*/\r
+ if (ep->xfer_len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ ep->xfer_len -= len;\r
+ }\r
+ else\r
+ {\r
+ len = ep->xfer_len;\r
+ ep->xfer_len = 0U;\r
+ }\r
+\r
+ /* configure and validate Tx endpoint */\r
+ if (ep->doublebuffer == 0U)\r
+ {\r
+ USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);\r
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);\r
+ }\r
+ else\r
+ {\r
+ /* Write the data to the USB endpoint */\r
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)\r
+ {\r
+ /* Set the Double buffer counter for pmabuffer1 */\r
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);\r
+ pmabuffer = ep->pmaaddr1;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Double buffer counter for pmabuffer0 */\r
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);\r
+ pmabuffer = ep->pmaaddr0;\r
+ }\r
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);\r
+ PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);\r
+ }\r
+\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);\r
+ }\r
+ else /* OUT endpoint */\r
+ {\r
+ /* Multi packet transfer*/\r
+ if (ep->xfer_len > ep->maxpacket)\r
+ {\r
+ len = ep->maxpacket;\r
+ ep->xfer_len -= len;\r
+ }\r
+ else\r
+ {\r
+ len = ep->xfer_len;\r
+ ep->xfer_len = 0U;\r
+ }\r
+\r
+ /* configure and validate Rx endpoint */\r
+ if (ep->doublebuffer == 0U)\r
+ {\r
+ /*Set RX buffer count*/\r
+ PCD_SET_EP_RX_CNT(USBx, ep->num, len);\r
+ }\r
+ else\r
+ {\r
+ /*Set the Double buffer counter*/\r
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);\r
+ }\r
+\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated\r
+ * with the EP/channel\r
+ * @param USBx : Selected device\r
+ * @param src : pointer to source buffer\r
+ * @param ch_ep_num : endpoint or host channel number\r
+ * @param len : Number of bytes to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(src);\r
+ UNUSED(ch_ep_num);\r
+ UNUSED(len);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated\r
+ * with the EP/channel\r
+ * @param USBx : Selected device\r
+ * @param dest : destination pointer\r
+ * @param len : Number of bytes to read\r
+ * @retval pointer to destination buffer\r
+ */\r
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(dest);\r
+ UNUSED(len);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return ((void *)NULL);\r
+}\r
+\r
+/**\r
+ * @brief USB_EPSetStall : set a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+ if (ep->is_in != 0U)\r
+ {\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);\r
+ }\r
+ else\r
+ {\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_EPClearStall : Clear a stall condition over an EP\r
+ * @param USBx : Selected device\r
+ * @param ep: pointer to endpoint structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)\r
+{\r
+ if (ep->doublebuffer == 0U)\r
+ {\r
+ if (ep->is_in != 0U)\r
+ {\r
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);\r
+\r
+ if (ep->type != EP_TYPE_ISOC)\r
+ {\r
+ /* Configure NAK status for the Endpoint */\r
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);\r
+\r
+ /* Configure VALID status for the Endpoint*/\r
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_StopDevice : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)\r
+{\r
+ /* disable all interrupts and force USB reset */\r
+ USBx->CNTR = USB_CNTR_FRES;\r
+\r
+ /* clear interrupt status register */\r
+ USBx->ISTR = 0;\r
+\r
+ /* switch-off device */\r
+ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_SetDevAddress : Stop the usb device mode\r
+ * @param USBx : Selected device\r
+ * @param address : new device address to be assigned\r
+ * This parameter can be a value from 0 to 255\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)\r
+{\r
+ if (address == 0U)\r
+ {\r
+ /* set device address and enable function */\r
+ USBx->DADDR = USB_DADDR_EF;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)\r
+{\r
+ /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */\r
+ USBx->BCDR |= USB_BCDR_DPPU;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)\r
+{\r
+ /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */\r
+ USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadInterrupts: return the global USB interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ tmpreg = USBx->ISTR;\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r
+ * @param USBx : Selected device\r
+ * @retval HAL status\r
+ */\r
+uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * @brief Returns Device OUT EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device OUT EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(epnum);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * @brief Returns Device IN EP Interrupt register\r
+ * @param USBx : Selected device\r
+ * @param epnum : endpoint number\r
+ * This parameter can be a value from 0 to 15\r
+ * @retval Device IN EP Interrupt register\r
+ */\r
+uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(epnum);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * @brief USB_ClearInterrupts: clear a USB interrupt\r
+ * @param USBx Selected device\r
+ * @param interrupt interrupt flag\r
+ * @retval None\r
+ */\r
+void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(interrupt);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Prepare the EP0 to start the first control setup\r
+ * @param USBx Selected device\r
+ * @param psetup pointer to setup packet\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(USBx);\r
+ UNUSED(psetup);\r
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used\r
+ only by USB OTG FS peripheral.\r
+ - This function is added to ensure compatibility across platforms.\r
+ */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)\r
+{\r
+ USBx->CNTR |= USB_CNTR_RESUME;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling\r
+ * @param USBx Selected device\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)\r
+{\r
+ USBx->CNTR &= ~(USB_CNTR_RESUME);\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
+ * @param USBx USB peripheral instance register address.\r
+ * @param pbUsrBuf pointer to user memory area.\r
+ * @param wPMABufAddr address into PMA.\r
+ * @param wNBytes: no. of bytes to be copied.\r
+ * @retval None\r
+ */\r
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
+{\r
+ uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;\r
+ uint32_t BaseAddr = (uint32_t)USBx;\r
+ uint32_t i, temp1, temp2;\r
+ uint16_t *pdwVal;\r
+ uint8_t *pBuf = pbUsrBuf;\r
+\r
+ pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
+\r
+ for (i = n; i != 0U; i--)\r
+ {\r
+ temp1 = (uint16_t) * pBuf;\r
+ pBuf++;\r
+ temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8));\r
+ *pdwVal = (uint16_t)temp2;\r
+ pdwVal++;\r
+\r
+#if PMA_ACCESS > 1U\r
+ pdwVal++;\r
+#endif\r
+\r
+ pBuf++;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)\r
+ * @param USBx: USB peripheral instance register address.\r
+ * @param pbUsrBuf pointer to user memory area.\r
+ * @param wPMABufAddr address into PMA.\r
+ * @param wNBytes: no. of bytes to be copied.\r
+ * @retval None\r
+ */\r
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)\r
+{\r
+ uint32_t n = (uint32_t)wNBytes >> 1;\r
+ uint32_t BaseAddr = (uint32_t)USBx;\r
+ uint32_t i, temp;\r
+ uint16_t *pdwVal;\r
+ uint8_t *pBuf = pbUsrBuf;\r
+\r
+ pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));\r
+\r
+ for (i = n; i != 0U; i--)\r
+ {\r
+ temp = *pdwVal;\r
+ pdwVal++;\r
+ *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
+ pBuf++;\r
+ *pBuf = (uint8_t)((temp >> 8) & 0xFFU);\r
+ pBuf++;\r
+\r
+#if PMA_ACCESS > 1U\r
+ pdwVal++;\r
+#endif\r
+ }\r
+\r
+ if ((wNBytes % 2U) != 0U)\r
+ {\r
+ temp = *pdwVal;\r
+ *pBuf = (uint8_t)((temp >> 0) & 0xFFU);\r
+ }\r
+}\r
+#endif /* defined (USB) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* defined (USB) || defined (USB_OTG_FS) */\r
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff