+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm33.h\r
- * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
- * @version V5.0.9\r
- * @date 06. July 2018\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined (__clang__)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM33_H_GENERIC\r
-#define __CORE_CM33_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M33\r
- @{\r
- */\r
-\r
-#include "cmsis_version.h"\r
-\r
-/* CMSIS CM33 definitions */\r
-#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
-#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
-#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (33U) /*!< Cortex-M Core */\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined (__TARGET_FPU_VFP)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
- #define __DSP_USED 1U\r
- #else\r
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
- #define __DSP_USED 0U\r
- #endif\r
- #else\r
- #define __DSP_USED 0U\r
- #endif\r
-\r
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined (__ARM_PCS_VFP)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
- #define __DSP_USED 1U\r
- #else\r
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
- #define __DSP_USED 0U\r
- #endif\r
- #else\r
- #define __DSP_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
- #define __DSP_USED 1U\r
- #else\r
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
- #define __DSP_USED 0U\r
- #endif\r
- #else\r
- #define __DSP_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined (__ARMVFP__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
- #define __DSP_USED 1U\r
- #else\r
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
- #define __DSP_USED 0U\r
- #endif\r
- #else\r
- #define __DSP_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TI_ARM__ )\r
- #if defined (__TI_VFP_SUPPORT__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined (__FPU_VFP__)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM33_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM33_H_DEPENDANT\r
-#define __CORE_CM33_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM33_REV\r
- #define __CM33_REV 0x0000U\r
- #warning "__CM33_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __SAUREGION_PRESENT\r
- #define __SAUREGION_PRESENT 0U\r
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DSP_PRESENT\r
- #define __DSP_PRESENT 0U\r
- #warning "__DSP_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M33 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core SAU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
-\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[16U];\r
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[16U];\r
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[16U];\r
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[16U];\r
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[16U];\r
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
- uint32_t RESERVED5[16U];\r
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED6[580U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
- uint32_t RESERVED3[92U];\r
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
- uint32_t RESERVED4[15U];\r
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
- uint32_t RESERVED5[1U];\r
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
- uint32_t RESERVED6[1U];\r
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
- uint32_t RESERVED7[6U];\r
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
- uint32_t RESERVED8[1U];\r
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
-\r
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
-\r
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
-\r
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
-\r
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
-\r
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
-\r
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
-\r
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
-\r
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
-\r
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
-\r
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
-\r
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
-\r
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
-\r
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
-\r
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
-\r
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
-\r
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
-\r
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
-\r
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
-\r
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
-\r
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
-\r
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
-\r
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
-\r
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
-\r
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
-\r
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
-\r
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* SCB Non-Secure Access Control Register Definitions */\r
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
-\r
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
-\r
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
-\r
-/* SCB Cache Level ID Register Definitions */\r
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* SCB Cache Type Register Definitions */\r
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* SCB Cache Size ID Register Definitions */\r
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* SCB Cache Size Selection Register Definitions */\r
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register Definitions */\r
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
-\r
-/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
-\r
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
-\r
-/* SCB D-Cache Clean by Set-way Register Definitions */\r
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
-\r
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
-\r
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
-\r
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Register Definitions */\r
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register Definitions */\r
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register Definitions */\r
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS Control Register Definitions */\r
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register Definitions */\r
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[1U];\r
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
- uint32_t RESERVED6[4U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Stimulus Port Register Definitions */\r
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
-\r
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
-\r
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- uint32_t RESERVED3[1U];\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED4[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- uint32_t RESERVED5[1U];\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED6[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- uint32_t RESERVED7[1U];\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
- uint32_t RESERVED8[1U];\r
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
- uint32_t RESERVED9[1U];\r
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
- uint32_t RESERVED10[1U];\r
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
- uint32_t RESERVED11[1U];\r
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
- uint32_t RESERVED12[1U];\r
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
- uint32_t RESERVED13[1U];\r
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
- uint32_t RESERVED14[1U];\r
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
- uint32_t RESERVED15[1U];\r
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
- uint32_t RESERVED16[1U];\r
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
- uint32_t RESERVED17[1U];\r
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
- uint32_t RESERVED18[1U];\r
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
- uint32_t RESERVED19[1U];\r
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
- uint32_t RESERVED20[1U];\r
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
- uint32_t RESERVED21[1U];\r
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
- uint32_t RESERVED22[1U];\r
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
- uint32_t RESERVED23[1U];\r
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
- uint32_t RESERVED24[1U];\r
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
- uint32_t RESERVED25[1U];\r
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
- uint32_t RESERVED26[1U];\r
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
- uint32_t RESERVED27[1U];\r
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
- uint32_t RESERVED28[1U];\r
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
- uint32_t RESERVED29[1U];\r
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
- uint32_t RESERVED30[1U];\r
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
- uint32_t RESERVED31[1U];\r
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
- uint32_t RESERVED32[934U];\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
- uint32_t RESERVED33[1U];\r
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
-\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
-\r
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
- __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */\r
- __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */\r
- __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
-\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
-#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */\r
-#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */\r
-#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */\r
-#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */\r
-#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
-\r
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
-\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
-\r
-/* TPI Integration Test ATB Control Register 0 Definitions */\r
-#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */\r
-#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
-\r
-#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */\r
-#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */\r
-#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
-\r
-#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */\r
-#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */\r
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
- uint32_t RESERVED0[1];\r
- union {\r
- __IOM uint32_t MAIR[2];\r
- struct {\r
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
- };\r
- };\r
-} MPU_Type;\r
-\r
-#define MPU_TYPE_RALIASES 4U\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
-\r
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
-\r
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
-\r
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
-\r
-/* MPU Region Limit Address Register Definitions */\r
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
-\r
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
-\r
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 0 Definitions */\r
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
-\r
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
-\r
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
-\r
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
-\r
-/* MPU Memory Attribute Indirection Register 1 Definitions */\r
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
-\r
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
-\r
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
-\r
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
- \brief Type definitions for the Security Attribution Unit (SAU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Security Attribution Unit (SAU).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
-#else\r
- uint32_t RESERVED0[3];\r
-#endif\r
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
-} SAU_Type;\r
-\r
-/* SAU Control Register Definitions */\r
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
-\r
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
-\r
-/* SAU Type Register Definitions */\r
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
-\r
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
-/* SAU Region Number Register Definitions */\r
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
-\r
-/* SAU Region Base Address Register Definitions */\r
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
-\r
-/* SAU Region Limit Address Register Definitions */\r
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
-\r
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
-\r
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
-\r
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
-\r
-/* Secure Fault Status Register Definitions */\r
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
-\r
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
-\r
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
-\r
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
-\r
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
-\r
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
-\r
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
-\r
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
-\r
-/*@} end of group CMSIS_SAU */\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
-\r
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
-\r
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
-\r
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
- uint32_t RESERVED4[1U];\r
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/* Debug Authentication Control Register Definitions */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
-\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
-\r
-/* Debug Security Control and Status Register Definitions */\r
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
-\r
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Core Hardware */\r
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
-\r
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
- #endif\r
-\r
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
- #endif\r
-\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
-\r
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
-\r
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
- #endif\r
-\r
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-#ifdef CMSIS_NVIC_VIRTUAL\r
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
- #endif\r
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
- #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
- #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
- #define NVIC_GetActive __NVIC_GetActive\r
- #define NVIC_SetPriority __NVIC_SetPriority\r
- #define NVIC_GetPriority __NVIC_GetPriority\r
- #define NVIC_SystemReset __NVIC_SystemReset\r
-#endif /* CMSIS_NVIC_VIRTUAL */\r
-\r
-#ifdef CMSIS_VECTAB_VIRTUAL\r
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
- #endif\r
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
-#else\r
- #define NVIC_SetVector __NVIC_SetVector\r
- #define NVIC_GetVector __NVIC_GetVector\r
-#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
-\r
-#define NVIC_USER_IRQ_OFFSET 16\r
-\r
-\r
-/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
-\r
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ \r
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
-\r
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
-#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
-\r
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
-#else \r
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
-#endif\r
-\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt\r
- \details Enables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status\r
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt\r
- \details Disables a device specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- __DSB();\r
- __ISB();\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Get Interrupt Target State\r
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 if interrupt is assigned to Secure\r
- \return 1 if interrupt is assigned to Non Secure\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Target State\r
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 if interrupt is assigned to Secure\r
- 1 if interrupt is assigned to Non Secure\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Interrupt Target State\r
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 if interrupt is assigned to Secure\r
- 1 if interrupt is assigned to Non Secure\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every processor exception.\r
- */\r
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of a device specific interrupt or a processor exception.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Vector\r
- \details Sets an interrupt vector in SRAM based interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- VTOR must been relocated to SRAM before.\r
- \param [in] IRQn Interrupt number\r
- \param [in] vector Address of interrupt handler function\r
- */\r
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Vector\r
- \details Reads an interrupt vector from interrupt vector table.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Address of interrupt handler function\r
- */\r
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
-{\r
- uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief Set Priority Grouping (non-secure)\r
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
- SCB_NS->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping (non-secure)\r
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
-{\r
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable Interrupt (non-secure)\r
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Enable status (non-secure)\r
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt is not enabled.\r
- \return 1 Interrupt is enabled.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Disable Interrupt (non-secure)\r
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt (non-secure)\r
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt (non-secure)\r
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt (non-secure)\r
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
- \param [in] IRQn Device specific interrupt number.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt (non-secure)\r
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
- \param [in] IRQn Device specific interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- \note IRQn must not be negative.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
- }\r
- else\r
- {\r
- return(0U);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority (non-secure)\r
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- \note The priority cannot be set for every non-secure processor exception.\r
- */\r
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority (non-secure)\r
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
- The interrupt number can be positive to specify a device specific interrupt,\r
- or negative to specify a processor exception.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) >= 0)\r
- {\r
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-/* ########################## MPU functions #################################### */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
-\r
-#include "mpu_armv8.h"\r
-\r
-#endif\r
-\r
-/* ########################## FPU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
- \brief Function that provides FPU type.\r
- @{\r
- */\r
-\r
-/**\r
- \brief get FPU type\r
- \details returns the FPU type\r
- \returns\r
- - \b 0: No FPU\r
- - \b 1: Single precision FPU\r
- - \b 2: Double + Single precision FPU\r
- */\r
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
-{\r
- uint32_t mvfr0;\r
-\r
- mvfr0 = FPU->MVFR0;\r
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
- {\r
- return 2U; /* Double + Single precision FPU */\r
- }\r
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
- {\r
- return 1U; /* Single precision FPU */\r
- }\r
- else\r
- {\r
- return 0U; /* No FPU */\r
- }\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_FpuFunctions */\r
-\r
-\r
-\r
-/* ########################## SAU functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
- \brief Functions that configure the SAU.\r
- @{\r
- */\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-\r
-/**\r
- \brief Enable SAU\r
- \details Enables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Enable(void)\r
-{\r
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-\r
-\r
-/**\r
- \brief Disable SAU\r
- \details Disables the Security Attribution Unit (SAU).\r
- */\r
-__STATIC_INLINE void TZ_SAU_Disable(void)\r
-{\r
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
-}\r
-\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-/*@} end of CMSIS_Core_SAUFunctions */\r
-\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
-/**\r
- \brief System Tick Configuration (non-secure)\r
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM33_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
projects / freertos / blobdiff