+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l4xx_hal.h\r
- * @author MCD Application Team\r
- * @brief This file contains all the functions prototypes for the HAL\r
- * module driver.\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef STM32L4xx_HAL_H\r
-#define STM32L4xx_HAL_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal_conf.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup HAL\r
- * @{\r
- */\r
-\r
-/* Exported types ------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-\r
-/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup HAL_TICK_FREQ Tick Frequency\r
- * @{\r
- */\r
-#define HAL_TICK_FREQ_10HZ 100U\r
-#define HAL_TICK_FREQ_100HZ 10U\r
-#define HAL_TICK_FREQ_1KHZ 1U\r
-#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup SYSCFG_BootMode Boot Mode\r
- * @{\r
- */\r
-#define SYSCFG_BOOT_MAINFLASH 0U\r
-#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
- defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
- /* STM32L496xx || STM32L4A6xx || */\r
- /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2)\r
-#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)\r
-#else\r
-#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts\r
- * @{\r
- */\r
-#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */\r
-#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */\r
-#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */\r
-#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */\r
-#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */\r
-#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)\r
- * @{\r
- */\r
-#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */\r
-#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */\r
-#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */\r
-#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */\r
-#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */\r
-#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */\r
-#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */\r
-#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */\r
-#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */\r
-#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */\r
-#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */\r
-#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */\r
-#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */\r
-#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */\r
-#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */\r
-#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */\r
-#if defined(SYSCFG_SWPR_PAGE31)\r
-#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */\r
-#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */\r
-#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */\r
-#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */\r
-#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */\r
-#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */\r
-#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */\r
-#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */\r
-#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */\r
-#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */\r
-#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */\r
-#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */\r
-#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */\r
-#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */\r
-#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */\r
-#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */\r
-#endif /* SYSCFG_SWPR_PAGE31 */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#if defined(SYSCFG_SWPR2_PAGE63)\r
-/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)\r
- * @{\r
- */\r
-#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */\r
-#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */\r
-#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */\r
-#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */\r
-#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */\r
-#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */\r
-#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */\r
-#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */\r
-#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */\r
-#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */\r
-#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */\r
-#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */\r
-#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */\r
-#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */\r
-#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */\r
-#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */\r
-#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */\r
-#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */\r
-#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */\r
-#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */\r
-#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */\r
-#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */\r
-#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */\r
-#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */\r
-#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */\r
-#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */\r
-#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */\r
-#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */\r
-#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */\r
-#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */\r
-#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */\r
-#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* SYSCFG_SWPR2_PAGE63 */\r
-\r
-#if defined(VREFBUF)\r
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale\r
- * @{\r
- */\r
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */\r
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance\r
- * @{\r
- */\r
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */\r
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */\r
-\r
-/**\r
- * @}\r
- */\r
-#endif /* VREFBUF */\r
-\r
-/** @defgroup SYSCFG_flags_definition Flags\r
- * @{\r
- */\r
-\r
-#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */\r
-#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO\r
- * @{\r
- */\r
-\r
-/** @brief Fast-mode Plus driving capability on a specific GPIO\r
- */\r
-#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */\r
-#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */\r
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\r
-#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */\r
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */\r
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)\r
-#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */\r
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported macros -----------------------------------------------------------*/\r
-\r
-/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief Freeze/Unfreeze Peripherals in Debug mode\r
- */\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)\r
-#endif\r
-\r
-#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros\r
- * @{\r
- */\r
-\r
-/** @brief Main Flash memory mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
-\r
-/** @brief System Flash memory mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)\r
-\r
-/** @brief Embedded SRAM mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))\r
-\r
-#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \\r
- defined (STM32L496xx) || defined (STM32L4A6xx) || \\r
- defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)\r
-\r
-#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */\r
- /* STM32L496xx || STM32L4A6xx || */\r
- /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)\r
-\r
-/** @brief OCTOSPI mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))\r
-#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))\r
-\r
-#else\r
-\r
-/** @brief QUADSPI mapped at 0x00000000.\r
- */\r
-#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))\r
-\r
-#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */\r
-\r
-/**\r
- * @brief Return the boot mode as configured by user.\r
- * @retval The boot mode as configured by user. The returned value can be one\r
- * of the following values:\r
- * @arg @ref SYSCFG_BOOT_MAINFLASH\r
- * @arg @ref SYSCFG_BOOT_SYSTEMFLASH\r
- @if STM32L486xx\r
- * @arg @ref SYSCFG_BOOT_FMC\r
- @endif\r
- * @arg @ref SYSCFG_BOOT_SRAM\r
- * @arg @ref SYSCFG_BOOT_QUADSPI\r
- */\r
-#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)\r
-\r
-/** @brief SRAM2 page 0 to 31 write protection enable macro\r
- * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP\r
- * @note Write protection can only be disabled by a system reset\r
- */\r
-#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
- SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\\r
- }while(0)\r
-\r
-#if defined(SYSCFG_SWPR2_PAGE63)\r
-/** @brief SRAM2 page 32 to 63 write protection enable macro\r
- * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63\r
- * @note Write protection can only be disabled by a system reset\r
- */\r
-#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\\r
- SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\\r
- }while(0)\r
-#endif /* SYSCFG_SWPR2_PAGE63 */\r
-\r
-/** @brief SRAM2 page write protection unlock prior to erase\r
- * @note Writing a wrong key reactivates the write protection\r
- */\r
-#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\\r
- SYSCFG->SKR = 0x53;\\r
- }while(0)\r
-\r
-/** @brief SRAM2 erase\r
- * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase\r
- */\r
-#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)\r
-\r
-/** @brief Floating Point Unit interrupt enable/disable macros\r
- * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts\r
- */\r
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
- SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
- }while(0)\r
-\r
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\\r
- CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\\r
- }while(0)\r
-\r
-/** @brief SYSCFG Break ECC lock.\r
- * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.\r
- * @note The selected configuration is locked and can be unlocked only by system reset.\r
- */\r
-#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)\r
-\r
-/** @brief SYSCFG Break Cortex-M4 Lockup lock.\r
- * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.\r
- * @note The selected configuration is locked and can be unlocked only by system reset.\r
- */\r
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)\r
-\r
-/** @brief SYSCFG Break PVD lock.\r
- * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.\r
- * @note The selected configuration is locked and can be unlocked only by system reset.\r
- */\r
-#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)\r
-\r
-/** @brief SYSCFG Break SRAM2 parity lock.\r
- * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.\r
- * @note The selected configuration is locked and can be unlocked by system reset.\r
- */\r
-#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)\r
-\r
-/** @brief Check SYSCFG flag is set or not.\r
- * @param __FLAG__ specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag\r
- * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing\r
- * @retval The new state of __FLAG__ (TRUE or FALSE).\r
- */\r
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)\r
-\r
-/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.\r
- */\r
-#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)\r
-\r
-/** @brief Fast-mode Plus driving capability enable/disable macros\r
- * @param __FASTMODEPLUS__ This parameter can be a value of :\r
- * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6\r
- * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7\r
- * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8\r
- * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9\r
- */\r
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
- SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
- }while(0)\r
-\r
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\\r
- CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\\r
- }while(0)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/** @defgroup HAL_Private_Macros HAL Private Macros\r
- * @{\r
- */\r
-\r
-#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \\r
- ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \\r
- ((__FREQ__) == HAL_TICK_FREQ_1KHZ))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros\r
- * @{\r
- */\r
-\r
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \\r
- (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \\r
- (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \\r
- (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \\r
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \\r
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))\r
-\r
-#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \\r
- ((__CONFIG__) == SYSCFG_BREAK_PVD) || \\r
- ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \\r
- ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))\r
-\r
-#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))\r
-\r
-#if defined(VREFBUF)\r
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \\r
- ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))\r
-\r
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \\r
- ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))\r
-\r
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))\r
-#endif /* VREFBUF */\r
-\r
-#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
-#elif defined(SYSCFG_FASTMODEPLUS_PB8)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))\r
-#elif defined(SYSCFG_FASTMODEPLUS_PB9)\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))\r
-#else\r
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \\r
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))\r
-#endif\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported variables --------------------------------------------------------*/\r
-\r
-/** @addtogroup HAL_Exported_Variables\r
- * @{\r
- */\r
-extern __IO uint32_t uwTick;\r
-extern uint32_t uwTickPrio;\r
-extern uint32_t uwTickFreq;\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-\r
-/** @addtogroup HAL_Exported_Functions\r
- * @{\r
- */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group1\r
- * @{\r
- */\r
-\r
-/* Initialization and de-initialization functions ******************************/\r
-HAL_StatusTypeDef HAL_Init(void);\r
-HAL_StatusTypeDef HAL_DeInit(void);\r
-void HAL_MspInit(void);\r
-void HAL_MspDeInit(void);\r
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group2\r
- * @{\r
- */\r
-\r
-/* Peripheral Control functions ************************************************/\r
-void HAL_IncTick(void);\r
-void HAL_Delay(uint32_t Delay);\r
-uint32_t HAL_GetTick(void);\r
-uint32_t HAL_GetTickPrio(void);\r
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);\r
-uint32_t HAL_GetTickFreq(void);\r
-void HAL_SuspendTick(void);\r
-void HAL_ResumeTick(void);\r
-uint32_t HAL_GetHalVersion(void);\r
-uint32_t HAL_GetREVID(void);\r
-uint32_t HAL_GetDEVID(void);\r
-uint32_t HAL_GetUIDw0(void);\r
-uint32_t HAL_GetUIDw1(void);\r
-uint32_t HAL_GetUIDw2(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group3\r
- * @{\r
- */\r
-\r
-/* DBGMCU Peripheral Control functions *****************************************/\r
-void HAL_DBGMCU_EnableDBGSleepMode(void);\r
-void HAL_DBGMCU_DisableDBGSleepMode(void);\r
-void HAL_DBGMCU_EnableDBGStopMode(void);\r
-void HAL_DBGMCU_DisableDBGStopMode(void);\r
-void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
-void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup HAL_Exported_Functions_Group4\r
- * @{\r
- */\r
-\r
-/* SYSCFG Control functions ****************************************************/\r
-void HAL_SYSCFG_SRAM2Erase(void);\r
-void HAL_SYSCFG_EnableMemorySwappingBank(void);\r
-void HAL_SYSCFG_DisableMemorySwappingBank(void);\r
-\r
-#if defined(VREFBUF)\r
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);\r
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);\r
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);\r
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);\r
-void HAL_SYSCFG_DisableVREFBUF(void);\r
-#endif /* VREFBUF */\r
-\r
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);\r
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* STM32L4xx_HAL_H */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
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