+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32l4xx_hal_spi.c\r
- * @author MCD Application Team\r
- * @brief SPI HAL module driver.\r
- * This file provides firmware functions to manage the following\r
- * functionalities of the Serial Peripheral Interface (SPI) peripheral:\r
- * + Initialization and de-initialization functions\r
- * + IO operation functions\r
- * + Peripheral Control functions\r
- * + Peripheral State functions\r
- *\r
- @verbatim\r
- ==============================================================================\r
- ##### How to use this driver #####\r
- ==============================================================================\r
- [..]\r
- The SPI HAL driver can be used as follows:\r
-\r
- (#) Declare a SPI_HandleTypeDef handle structure, for example:\r
- SPI_HandleTypeDef hspi;\r
-\r
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r
- (##) Enable the SPIx interface clock\r
- (##) SPI pins configuration\r
- (+++) Enable the clock for the SPI GPIOs\r
- (+++) Configure these SPI pins as alternate function push-pull\r
- (##) NVIC configuration if you need to use interrupt process\r
- (+++) Configure the SPIx interrupt priority\r
- (+++) Enable the NVIC SPI IRQ handle\r
- (##) DMA Configuration if you need to use DMA process\r
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel\r
- (+++) Enable the DMAx clock\r
- (+++) Configure the DMA handle parameters\r
- (+++) Configure the DMA Tx or Rx Stream/Channel\r
- (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle\r
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel\r
-\r
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r
-\r
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r
- by calling the customized HAL_SPI_MspInit() API.\r
- [..]\r
- Circular mode restriction:\r
- (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r
- (##) Master 2Lines RxOnly\r
- (##) Master 1Line Rx\r
- (#) The CRC feature is not managed when the DMA circular mode is enabled\r
- (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r
- the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r
- [..]\r
- Master Receive mode restriction:\r
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or\r
- bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI\r
- does not initiate a new transfer the following procedure has to be respected:\r
- (##) HAL_SPI_DeInit()\r
- (##) HAL_SPI_Init()\r
- [..]\r
- Callback registration:\r
-\r
- (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U\r
- allows the user to configure dynamically the driver callbacks.\r
- Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.\r
-\r
- Function HAL_SPI_RegisterCallback() allows to register following callbacks:\r
- (+) TxCpltCallback : SPI Tx Completed callback\r
- (+) RxCpltCallback : SPI Rx Completed callback\r
- (+) TxRxCpltCallback : SPI TxRx Completed callback\r
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback\r
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback\r
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback\r
- (+) ErrorCallback : SPI Error callback\r
- (+) AbortCpltCallback : SPI Abort callback\r
- (+) MspInitCallback : SPI Msp Init callback\r
- (+) MspDeInitCallback : SPI Msp DeInit callback\r
- This function takes as parameters the HAL peripheral handle, the Callback ID\r
- and a pointer to the user callback function.\r
-\r
-\r
- (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default\r
- weak function.\r
- HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
- and the Callback ID.\r
- This function allows to reset following callbacks:\r
- (+) TxCpltCallback : SPI Tx Completed callback\r
- (+) RxCpltCallback : SPI Rx Completed callback\r
- (+) TxRxCpltCallback : SPI TxRx Completed callback\r
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback\r
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback\r
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback\r
- (+) ErrorCallback : SPI Error callback\r
- (+) AbortCpltCallback : SPI Abort callback\r
- (+) MspInitCallback : SPI Msp Init callback\r
- (+) MspDeInitCallback : SPI Msp DeInit callback\r
-\r
- By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET\r
- all callbacks are set to the corresponding weak functions:\r
- examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().\r
- Exception done for MspInit and MspDeInit functions that are\r
- reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when\r
- these callbacks are null (not registered beforehand).\r
- If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()\r
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
-\r
- Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.\r
- Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
- in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,\r
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
- Then, the user first registers the MspInit/MspDeInit user callbacks\r
- using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()\r
- or HAL_SPI_Init() function.\r
-\r
- When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or\r
- not defined, the callback registering feature is not available\r
- and weak (surcharged) callbacks are used.\r
-\r
- [..]\r
- Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,\r
- the following table resume the max SPI frequency reached with data size 8bits/16bits,\r
- according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.\r
-\r
- @endverbatim\r
-\r
- Additional table :\r
-\r
- DataSize = SPI_DATASIZE_8BIT:\r
- +----------------------------------------------------------------------------------------------+\r
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |\r
- | Process | Tranfert mode |---------------------|----------------------|----------------------|\r
- | | | Master | Slave | Master | Slave | Master | Slave |\r
- |==============================================================================================|\r
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |\r
- | R |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |\r
- |=========|================|==========|==========|===========|==========|===========|==========|\r
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |\r
- | |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |\r
- |=========|================|==========|==========|===========|==========|===========|==========|\r
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |\r
- | |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |\r
- +----------------------------------------------------------------------------------------------+\r
-\r
- DataSize = SPI_DATASIZE_16BIT:\r
- +----------------------------------------------------------------------------------------------+\r
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |\r
- | Process | Tranfert mode |---------------------|----------------------|----------------------|\r
- | | | Master | Slave | Master | Slave | Master | Slave |\r
- |==============================================================================================|\r
- | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |\r
- | R |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |\r
- |=========|================|==========|==========|===========|==========|===========|==========|\r
- | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |\r
- | |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |\r
- |=========|================|==========|==========|===========|==========|===========|==========|\r
- | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |\r
- | |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |\r
- | X |----------------|----------|----------|-----------|----------|-----------|----------|\r
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |\r
- +----------------------------------------------------------------------------------------------+\r
- @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),\r
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\r
- @note\r
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\r
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\r
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\r
-\r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
- * All rights reserved.</center></h2>\r
- *\r
- * This software component is licensed by ST under BSD 3-Clause license,\r
- * the "License"; You may not use this file except in compliance with the\r
- * License. You may obtain a copy of the License at:\r
- * opensource.org/licenses/BSD-3-Clause\r
- *\r
- ******************************************************************************\r
- */\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32l4xx_hal.h"\r
-\r
-/** @addtogroup STM32L4xx_HAL_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI SPI\r
- * @brief SPI HAL module driver\r
- * @{\r
- */\r
-#ifdef HAL_SPI_MODULE_ENABLED\r
-\r
-/* Private typedef -----------------------------------------------------------*/\r
-/* Private defines -----------------------------------------------------------*/\r
-/** @defgroup SPI_Private_Constants SPI Private Constants\r
- * @{\r
- */\r
-#define SPI_DEFAULT_TIMEOUT 100U\r
-/**\r
- * @}\r
- */\r
-\r
-/* Private macros ------------------------------------------------------------*/\r
-/* Private variables ---------------------------------------------------------*/\r
-/* Private function prototypes -----------------------------------------------*/\r
-/** @defgroup SPI_Private_Functions SPI Private Functions\r
- * @{\r
- */\r
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAError(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
- uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
- uint32_t Timeout, uint32_t Tickstart);\r
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r
-#if (USE_SPI_CRC != 0U)\r
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r
-#endif /* USE_SPI_CRC */\r
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r
-/**\r
- * @}\r
- */\r
-\r
-/* Exported functions --------------------------------------------------------*/\r
-/** @defgroup SPI_Exported_Functions SPI Exported Functions\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r
- * @brief Initialization and Configuration functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Initialization and de-initialization functions #####\r
- ===============================================================================\r
- [..] This subsection provides a set of functions allowing to initialize and\r
- de-initialize the SPIx peripheral:\r
-\r
- (+) User must implement HAL_SPI_MspInit() function in which he configures\r
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
-\r
- (+) Call the function HAL_SPI_Init() to configure the selected device with\r
- the selected configuration:\r
- (++) Mode\r
- (++) Direction\r
- (++) Data Size\r
- (++) Clock Polarity and Phase\r
- (++) NSS Management\r
- (++) BaudRate Prescaler\r
- (++) FirstBit\r
- (++) TIMode\r
- (++) CRC Calculation\r
- (++) CRC Polynomial if CRC enabled\r
- (++) CRC Length, used only with Data8 and Data16\r
- (++) FIFO reception threshold\r
-\r
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r
- of the selected SPIx peripheral.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Initialize the SPI according to the specified parameters\r
- * in the SPI_InitTypeDef and initialize the associated handle.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r
-{\r
- uint32_t frxth;\r
-\r
- /* Check the SPI handle allocation */\r
- if (hspi == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
- assert_param(IS_SPI_MODE(hspi->Init.Mode));\r
- assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r
- assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r
- assert_param(IS_SPI_NSS(hspi->Init.NSS));\r
- assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r
- assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r
- assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r
- if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)\r
- {\r
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r
- }\r
-#if (USE_SPI_CRC != 0U)\r
- assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r
- }\r
-#else\r
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->State == HAL_SPI_STATE_RESET)\r
- {\r
- /* Allocate lock resource and initialize it */\r
- hspi->Lock = HAL_UNLOCKED;\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- /* Init the SPI Callback settings */\r
- hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
- hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
- hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */\r
- hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
- hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
- hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
- hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */\r
- hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
-\r
- if (hspi->MspInitCallback == NULL)\r
- {\r
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */\r
- }\r
-\r
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
- hspi->MspInitCallback(hspi);\r
-#else\r
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r
- HAL_SPI_MspInit(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
-\r
- hspi->State = HAL_SPI_STATE_BUSY;\r
-\r
- /* Disable the selected SPI peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- /* Align by default the rs fifo threshold on the data size */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- frxth = SPI_RXFIFO_THRESHOLD_HF;\r
- }\r
- else\r
- {\r
- frxth = SPI_RXFIFO_THRESHOLD_QF;\r
- }\r
-\r
- /* CRC calculation is valid only for 16Bit and 8 Bit */\r
- if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))\r
- {\r
- /* CRC must be disabled */\r
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r
- }\r
-\r
- /* Align the CRC Length on the data size */\r
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r
- {\r
- /* CRC Length aligned on the data size : value set by default */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r
- }\r
- else\r
- {\r
- hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r
- }\r
- }\r
-\r
- /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\r
- /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r
- Communication speed, First bit and CRC calculation state */\r
- WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |\r
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));\r
-#if (USE_SPI_CRC != 0U)\r
- /* Configure : CRC Length */\r
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
- {\r
- hspi->Instance->CR1 |= SPI_CR1_CRCL;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */\r
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |\r
- hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\r
- /* Configure : CRC Polynomial */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
-#if defined(SPI_I2SCFGR_I2SMOD)\r
- /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\r
- CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\r
-#endif /* SPI_I2SCFGR_I2SMOD */\r
-\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief De-Initialize the SPI peripheral.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Check the SPI handle allocation */\r
- if (hspi == NULL)\r
- {\r
- return HAL_ERROR;\r
- }\r
-\r
- /* Check SPI Instance parameter */\r
- assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r
-\r
- hspi->State = HAL_SPI_STATE_BUSY;\r
-\r
- /* Disable the SPI Peripheral Clock */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- if (hspi->MspDeInitCallback == NULL)\r
- {\r
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */\r
- }\r
-\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
- hspi->MspDeInitCallback(hspi);\r
-#else\r
- /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r
- HAL_SPI_MspDeInit(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->State = HAL_SPI_STATE_RESET;\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(hspi);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Initialize the SPI MSP.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_MspInit should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief De-Initialize the SPI MSP.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_MspDeInit should be implemented in the user file\r
- */\r
-}\r
-\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
-/**\r
- * @brief Register a User SPI Callback\r
- * To be used instead of the weak predefined callback\r
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI.\r
- * @param CallbackID ID of the callback to be registered\r
- * @param pCallback pointer to the Callback function\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- if (pCallback == NULL)\r
- {\r
- /* Update the error code */\r
- hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;\r
-\r
- return HAL_ERROR;\r
- }\r
- /* Process locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if (HAL_SPI_STATE_READY == hspi->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_SPI_TX_COMPLETE_CB_ID :\r
- hspi->TxCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_RX_COMPLETE_CB_ID :\r
- hspi->RxCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
- hspi->TxRxCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
- hspi->TxHalfCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
- hspi->RxHalfCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
- hspi->TxRxHalfCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_ERROR_CB_ID :\r
- hspi->ErrorCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_ABORT_CB_ID :\r
- hspi->AbortCpltCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_MSPINIT_CB_ID :\r
- hspi->MspInitCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_MSPDEINIT_CB_ID :\r
- hspi->MspDeInitCallback = pCallback;\r
- break;\r
-\r
- default :\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- break;\r
- }\r
- }\r
- else if (HAL_SPI_STATE_RESET == hspi->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_SPI_MSPINIT_CB_ID :\r
- hspi->MspInitCallback = pCallback;\r
- break;\r
-\r
- case HAL_SPI_MSPDEINIT_CB_ID :\r
- hspi->MspDeInitCallback = pCallback;\r
- break;\r
-\r
- default :\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- }\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(hspi);\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Unregister an SPI Callback\r
- * SPI callback is redirected to the weak predefined callback\r
- * @param hspi Pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI.\r
- * @param CallbackID ID of the callback to be unregistered\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)\r
-{\r
- HAL_StatusTypeDef status = HAL_OK;\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if (HAL_SPI_STATE_READY == hspi->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_SPI_TX_COMPLETE_CB_ID :\r
- hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_RX_COMPLETE_CB_ID :\r
- hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_TX_RX_COMPLETE_CB_ID :\r
- hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\r
- hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\r
- hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\r
- hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_ERROR_CB_ID :\r
- hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */\r
- break;\r
-\r
- case HAL_SPI_ABORT_CB_ID :\r
- hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
- break;\r
-\r
- case HAL_SPI_MSPINIT_CB_ID :\r
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */\r
- break;\r
-\r
- case HAL_SPI_MSPDEINIT_CB_ID :\r
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */\r
- break;\r
-\r
- default :\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- break;\r
- }\r
- }\r
- else if (HAL_SPI_STATE_RESET == hspi->State)\r
- {\r
- switch (CallbackID)\r
- {\r
- case HAL_SPI_MSPINIT_CB_ID :\r
- hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */\r
- break;\r
-\r
- case HAL_SPI_MSPDEINIT_CB_ID :\r
- hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */\r
- break;\r
-\r
- default :\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /* Update the error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\r
-\r
- /* Return error status */\r
- status = HAL_ERROR;\r
- }\r
-\r
- /* Release Lock */\r
- __HAL_UNLOCK(hspi);\r
- return status;\r
-}\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r
- * @brief Data transfers functions\r
- *\r
-@verbatim\r
- ==============================================================================\r
- ##### IO operation functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to manage the SPI\r
- data transfers.\r
-\r
- [..] The SPI supports master and slave mode :\r
-\r
- (#) There are two modes of transfer:\r
- (++) Blocking mode: The communication is performed in polling mode.\r
- The HAL status of all data processing is returned by the same function\r
- after finishing transfer.\r
- (++) No-Blocking mode: The communication is performed using Interrupts\r
- or DMA, These APIs return the HAL status.\r
- The end of the data processing will be indicated through the\r
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r
- using DMA mode.\r
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r
- will be executed respectively at the end of the transmit or Receive process\r
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r
-\r
- (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r
- exist for 1Line (simplex) and 2Lines (full duplex) modes.\r
-\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Transmit an amount of data in blocking mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @param Size amount of data to be sent\r
- * @param Timeout Timeout duration\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
- uint32_t tickstart;\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
- uint16_t initial_TxXferCount;\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
- initial_TxXferCount = Size;\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_TX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pTxBuffPtr = (uint8_t *)pData;\r
- hspi->TxXferSize = Size;\r
- hspi->TxXferCount = Size;\r
-\r
- /*Init field not used in handle to zero */\r
- hspi->pRxBuffPtr = (uint8_t *)NULL;\r
- hspi->RxXferSize = 0U;\r
- hspi->RxXferCount = 0U;\r
- hspi->TxISR = NULL;\r
- hspi->RxISR = NULL;\r
-\r
- /* Configure communication direction : 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_TX(hspi);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
- /* Transmit data in 16 Bit mode */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
- }\r
- /* Transmit data in 16 Bit mode */\r
- while (hspi->TxXferCount > 0U)\r
- {\r
- /* Wait until TXE flag is set to send data */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
- }\r
- else\r
- {\r
- /* Timeout management */\r
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
- }\r
- /* Transmit data in 8 Bit mode */\r
- else\r
- {\r
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
- {\r
- if (hspi->TxXferCount > 1U)\r
- {\r
- /* write on the data register in packing mode */\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount -= 2U;\r
- }\r
- else\r
- {\r
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr ++;\r
- hspi->TxXferCount--;\r
- }\r
- }\r
- while (hspi->TxXferCount > 0U)\r
- {\r
- /* Wait until TXE flag is set to send data */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r
- {\r
- if (hspi->TxXferCount > 1U)\r
- {\r
- /* write on the data register in packing mode */\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount -= 2U;\r
- }\r
- else\r
- {\r
- *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr++;\r
- hspi->TxXferCount--;\r
- }\r
- }\r
- else\r
- {\r
- /* Timeout management */\r
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
- }\r
-#if (USE_SPI_CRC != 0U)\r
- /* Enable CRC Transmission */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
- }\r
-\r
- /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
- {\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- }\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- errorcode = HAL_ERROR;\r
- }\r
-\r
-error:\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Receive an amount of data in blocking mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @param Size amount of data to be received\r
- * @param Timeout Timeout duration\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
-{\r
- uint32_t tickstart;\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);\r
- }\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pRxBuffPtr = (uint8_t *)pData;\r
- hspi->RxXferSize = Size;\r
- hspi->RxXferCount = Size;\r
-\r
- /*Init field not used in handle to zero */\r
- hspi->pTxBuffPtr = (uint8_t *)NULL;\r
- hspi->TxXferSize = 0U;\r
- hspi->TxXferCount = 0U;\r
- hspi->RxISR = NULL;\r
- hspi->TxISR = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- /* this is done to handle the CRCNEXT before the latest data */\r
- hspi->RxXferCount--;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Set the Rx Fifo threshold */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
-\r
- /* Configure communication direction: 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_RX(hspi);\r
- }\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
- /* Receive data in 8 Bit mode */\r
- if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r
- {\r
- /* Transfer loop */\r
- while (hspi->RxXferCount > 0U)\r
- {\r
- /* Check the RXNE flag */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
- {\r
- /* read the received data */\r
- (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
- hspi->pRxBuffPtr += sizeof(uint8_t);\r
- hspi->RxXferCount--;\r
- }\r
- else\r
- {\r
- /* Timeout management */\r
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Transfer loop */\r
- while (hspi->RxXferCount > 0U)\r
- {\r
- /* Check the RXNE flag */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r
- {\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount--;\r
- }\r
- else\r
- {\r
- /* Timeout management */\r
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Handle the CRC Transmission */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* freeze the CRC before the latest data */\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
-\r
- /* Read the latest data */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
- {\r
- /* the latest data has not been received */\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
-\r
- /* Receive last data in 16 Bit mode */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
- }\r
- /* Receive last data in 8 Bit mode */\r
- else\r
- {\r
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
- }\r
-\r
- /* Wait the CRC data */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
-\r
- /* Read CRC to Flush DR and RXNE flag */\r
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
- {\r
- /* Read 16bit CRC */\r
- READ_REG(hspi->Instance->DR);\r
- }\r
- else\r
- {\r
- /* Read 8bit CRC */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
- {\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
- }\r
- }\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- errorcode = HAL_ERROR;\r
- }\r
-\r
-error :\r
- hspi->State = HAL_SPI_STATE_READY;\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Transmit and Receive an amount of data in blocking mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pTxData pointer to transmission data buffer\r
- * @param pRxData pointer to reception data buffer\r
- * @param Size amount of data to be sent and received\r
- * @param Timeout Timeout duration\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r
- uint32_t Timeout)\r
-{\r
- uint16_t initial_TxXferCount;\r
- uint16_t initial_RxXferCount;\r
- uint32_t tmp_mode;\r
- HAL_SPI_StateTypeDef tmp_state;\r
- uint32_t tickstart;\r
-#if (USE_SPI_CRC != 0U)\r
- uint32_t spi_cr1;\r
- uint32_t spi_cr2;\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Variable used to alternate Rx and Tx during transfer */\r
- uint32_t txallowed = 1U;\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Init temporary variables */\r
- tmp_state = hspi->State;\r
- tmp_mode = hspi->Init.Mode;\r
- initial_TxXferCount = Size;\r
- initial_RxXferCount = Size;\r
-#if (USE_SPI_CRC != 0U)\r
- spi_cr1 = READ_REG(hspi->Instance->CR1);\r
- spi_cr2 = READ_REG(hspi->Instance->CR2);\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
- hspi->RxXferCount = Size;\r
- hspi->RxXferSize = Size;\r
- hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
- hspi->TxXferCount = Size;\r
- hspi->TxXferSize = Size;\r
-\r
- /*Init field not used in handle to zero */\r
- hspi->RxISR = NULL;\r
- hspi->TxISR = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Set the Rx Fifo threshold */\r
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))\r
- {\r
- /* Set fiforxthreshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set fiforxthreshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
- /* Transmit and Receive data in 16 Bit mode */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
- }\r
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
- {\r
- /* Check TXE flag */\r
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
- /* Next Data is a reception (Rx). Tx not allowed */\r
- txallowed = 0U;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Enable CRC Transmission */\r
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
- {\r
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
- if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
- {\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
- }\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
- }\r
-\r
- /* Check RXNE flag */\r
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
- {\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount--;\r
- /* Next Data is a Transmission (Tx). Tx is allowed */\r
- txallowed = 1U;\r
- }\r
- if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
- /* Transmit and Receive data in 8 Bit mode */\r
- else\r
- {\r
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\r
- {\r
- if (hspi->TxXferCount > 1U)\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount -= 2U;\r
- }\r
- else\r
- {\r
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr++;\r
- hspi->TxXferCount--;\r
- }\r
- }\r
- while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r
- {\r
- /* Check TXE flag */\r
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\r
- {\r
- if (hspi->TxXferCount > 1U)\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount -= 2U;\r
- }\r
- else\r
- {\r
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr++;\r
- hspi->TxXferCount--;\r
- }\r
- /* Next Data is a reception (Rx). Tx not allowed */\r
- txallowed = 0U;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Enable CRC Transmission */\r
- if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
- {\r
- /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r
- if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))\r
- {\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r
- }\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
- }\r
-\r
- /* Wait until RXNE flag is reset */\r
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\r
- {\r
- if (hspi->RxXferCount > 1U)\r
- {\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount -= 2U;\r
- if (hspi->RxXferCount <= 1U)\r
- {\r
- /* Set RX Fifo threshold before to switch on 8 bit data size */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- }\r
- else\r
- {\r
- (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\r
- hspi->pRxBuffPtr++;\r
- hspi->RxXferCount--;\r
- }\r
- /* Next Data is a Transmission (Tx). Tx is allowed */\r
- txallowed = 1U;\r
- }\r
- if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))\r
- {\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- }\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Read CRC from DR to close CRC calculation process */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Wait until TXE flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- /* Read CRC */\r
- if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r
- {\r
- /* Read 16bit CRC */\r
- READ_REG(hspi->Instance->DR);\r
- }\r
- else\r
- {\r
- /* Read 8bit CRC */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
- {\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- errorcode = HAL_TIMEOUT;\r
- goto error;\r
- }\r
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
- }\r
- }\r
- }\r
-\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- /* Clear CRC Flag */\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
-\r
- errorcode = HAL_ERROR;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r
- {\r
- errorcode = HAL_ERROR;\r
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
- }\r
-\r
-error :\r
- hspi->State = HAL_SPI_STATE_READY;\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Transmit an amount of data in non-blocking mode with Interrupt.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @param Size amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_TX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pTxBuffPtr = (uint8_t *)pData;\r
- hspi->TxXferSize = Size;\r
- hspi->TxXferCount = Size;\r
-\r
- /* Init field not used in handle to zero */\r
- hspi->pRxBuffPtr = (uint8_t *)NULL;\r
- hspi->RxXferSize = 0U;\r
- hspi->RxXferCount = 0U;\r
- hspi->RxISR = NULL;\r
-\r
- /* Set the function for IT treatment */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- hspi->TxISR = SPI_TxISR_16BIT;\r
- }\r
- else\r
- {\r
- hspi->TxISR = SPI_TxISR_8BIT;\r
- }\r
-\r
- /* Configure communication direction : 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_TX(hspi);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Enable TXE and ERR interrupt */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
-\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
-error :\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Receive an amount of data in non-blocking mode with Interrupt.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @param Size amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\r
- }\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pRxBuffPtr = (uint8_t *)pData;\r
- hspi->RxXferSize = Size;\r
- hspi->RxXferCount = Size;\r
-\r
- /* Init field not used in handle to zero */\r
- hspi->pTxBuffPtr = (uint8_t *)NULL;\r
- hspi->TxXferSize = 0U;\r
- hspi->TxXferCount = 0U;\r
- hspi->TxISR = NULL;\r
-\r
- /* Check the data size to adapt Rx threshold and the set the function for IT treatment */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16 bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- hspi->RxISR = SPI_RxISR_16BIT;\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8 bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- hspi->RxISR = SPI_RxISR_8BIT;\r
- }\r
-\r
- /* Configure communication direction : 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_RX(hspi);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- hspi->CRCSize = 1U;\r
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
- {\r
- hspi->CRCSize = 2U;\r
- }\r
- SPI_RESET_CRC(hspi);\r
- }\r
- else\r
- {\r
- hspi->CRCSize = 0U;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Enable TXE and ERR interrupt */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- /* Note : The SPI must be enabled after unlocking current process\r
- to avoid the risk of SPI interrupt handle execution before current\r
- process unlock */\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
-error :\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pTxData pointer to transmission data buffer\r
- * @param pRxData pointer to reception data buffer\r
- * @param Size amount of data to be sent and received\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r
-{\r
- uint32_t tmp_mode;\r
- HAL_SPI_StateTypeDef tmp_state;\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Init temporary variables */\r
- tmp_state = hspi->State;\r
- tmp_mode = hspi->Init.Mode;\r
-\r
- if (!((tmp_state == HAL_SPI_STATE_READY) || \\r
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
- hspi->TxXferSize = Size;\r
- hspi->TxXferCount = Size;\r
- hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
- hspi->RxXferSize = Size;\r
- hspi->RxXferCount = Size;\r
-\r
- /* Set the function for IT treatment */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- hspi->RxISR = SPI_2linesRxISR_16BIT;\r
- hspi->TxISR = SPI_2linesTxISR_16BIT;\r
- }\r
- else\r
- {\r
- hspi->RxISR = SPI_2linesRxISR_8BIT;\r
- hspi->TxISR = SPI_2linesTxISR_8BIT;\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- hspi->CRCSize = 1U;\r
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r
- {\r
- hspi->CRCSize = 2U;\r
- }\r
- SPI_RESET_CRC(hspi);\r
- }\r
- else\r
- {\r
- hspi->CRCSize = 0U;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check if packing mode is enabled and if there is more than 2 data to receive */\r
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16 bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8 bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
-\r
- /* Enable TXE, RXNE and ERR interrupt */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
-error :\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Transmit an amount of data in non-blocking mode with DMA.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @param Size amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check tx dma handle */\r
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_TX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pTxBuffPtr = (uint8_t *)pData;\r
- hspi->TxXferSize = Size;\r
- hspi->TxXferCount = Size;\r
-\r
- /* Init field not used in handle to zero */\r
- hspi->pRxBuffPtr = (uint8_t *)NULL;\r
- hspi->TxISR = NULL;\r
- hspi->RxISR = NULL;\r
- hspi->RxXferSize = 0U;\r
- hspi->RxXferCount = 0U;\r
-\r
- /* Configure communication direction : 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_TX(hspi);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Set the SPI TxDMA Half transfer complete callback */\r
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r
-\r
- /* Set the SPI TxDMA transfer complete callback */\r
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r
-\r
- /* Set the DMA error callback */\r
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r
-\r
- /* Set the DMA AbortCpltCallback */\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- /* Packing mode is enabled only if the DMA setting is HALWORD */\r
- if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r
- {\r
- /* Check the even/odd of the data size + crc if enabled */\r
- if ((hspi->TxXferCount & 0x1U) == 0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = (hspi->TxXferCount >> 1U);\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
- }\r
- }\r
-\r
- /* Enable the Tx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
- {\r
- /* Update SPI error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- goto error;\r
- }\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
- /* Enable the SPI Error Interrupt Bit */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
- /* Enable Tx DMA Request */\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-error :\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Receive an amount of data in non-blocking mode with DMA.\r
- * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pData pointer to data buffer\r
- * @note When the CRC feature is enabled the pData Length must be Size + 1.\r
- * @param Size amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r
-{\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check rx dma handle */\r
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
-\r
- if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
-\r
- /* Check tx dma handle */\r
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\r
- }\r
-\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- if (hspi->State != HAL_SPI_STATE_READY)\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->State = HAL_SPI_STATE_BUSY_RX;\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pRxBuffPtr = (uint8_t *)pData;\r
- hspi->RxXferSize = Size;\r
- hspi->RxXferCount = Size;\r
-\r
- /*Init field not used in handle to zero */\r
- hspi->RxISR = NULL;\r
- hspi->TxISR = NULL;\r
- hspi->TxXferSize = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Configure communication direction : 1Line */\r
- if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- {\r
- SPI_1LINE_RX(hspi);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
-\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
- }\r
- }\r
- }\r
-\r
- /* Set the SPI RxDMA Half transfer complete callback */\r
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
-\r
- /* Set the SPI Rx DMA transfer complete callback */\r
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
-\r
- /* Set the DMA error callback */\r
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
-\r
- /* Set the DMA AbortCpltCallback */\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
- /* Enable the Rx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
- {\r
- /* Update SPI error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- goto error;\r
- }\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
-\r
- /* Enable the SPI Error Interrupt Bit */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
- /* Enable Rx DMA Request */\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
-error:\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param pTxData pointer to transmission data buffer\r
- * @param pRxData pointer to reception data buffer\r
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1\r
- * @param Size amount of data to be sent\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r
- uint16_t Size)\r
-{\r
- uint32_t tmp_mode;\r
- HAL_SPI_StateTypeDef tmp_state;\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
-\r
- /* Check rx & tx dma handles */\r
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\r
- assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\r
-\r
- /* Check Direction parameter */\r
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r
-\r
- /* Process locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Init temporary variables */\r
- tmp_state = hspi->State;\r
- tmp_mode = hspi->Init.Mode;\r
-\r
- if (!((tmp_state == HAL_SPI_STATE_READY) ||\r
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\r
- {\r
- errorcode = HAL_BUSY;\r
- goto error;\r
- }\r
-\r
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r
- {\r
- errorcode = HAL_ERROR;\r
- goto error;\r
- }\r
-\r
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r
- if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r
- {\r
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r
- }\r
-\r
- /* Set the transaction information */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- hspi->pTxBuffPtr = (uint8_t *)pTxData;\r
- hspi->TxXferSize = Size;\r
- hspi->TxXferCount = Size;\r
- hspi->pRxBuffPtr = (uint8_t *)pRxData;\r
- hspi->RxXferSize = Size;\r
- hspi->RxXferCount = Size;\r
-\r
- /* Init field not used in handle to zero */\r
- hspi->RxISR = NULL;\r
- hspi->TxISR = NULL;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Reset the threshold bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r
-\r
- /* The packing mode management is enabled by the DMA settings according the spi data size */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Set fiforxthreshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- else\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
- {\r
- if ((hspi->TxXferSize & 0x1U) == 0x0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = hspi->TxXferCount >> 1U;\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r
- hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r
- }\r
- }\r
-\r
- if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 16bit */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
-\r
- if ((hspi->RxXferCount & 0x1U) == 0x0U)\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = hspi->RxXferCount >> 1U;\r
- }\r
- else\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r
- hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r
- }\r
- }\r
- }\r
-\r
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\r
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
- {\r
- /* Set the SPI Rx DMA Half transfer complete callback */\r
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r
- }\r
- else\r
- {\r
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */\r
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r
- }\r
-\r
- /* Set the DMA error callback */\r
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r
-\r
- /* Set the DMA AbortCpltCallback */\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
- /* Enable the Rx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))\r
- {\r
- /* Update SPI error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- goto error;\r
- }\r
-\r
- /* Enable Rx DMA Request */\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r
- is performed in DMA reception complete callback */\r
- hspi->hdmatx->XferHalfCpltCallback = NULL;\r
- hspi->hdmatx->XferCpltCallback = NULL;\r
- hspi->hdmatx->XferErrorCallback = NULL;\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
- /* Enable the Tx DMA Stream/Channel */\r
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))\r
- {\r
- /* Update SPI error code */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- goto error;\r
- }\r
-\r
- /* Check if the SPI is already enabled */\r
- if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r
- {\r
- /* Enable SPI peripheral */\r
- __HAL_SPI_ENABLE(hspi);\r
- }\r
- /* Enable the SPI Error Interrupt Bit */\r
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r
-\r
- /* Enable Tx DMA Request */\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
-error :\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Abort ongoing transfer (blocking mode).\r
- * @param hspi SPI handle.\r
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
- * started in Interrupt or DMA mode.\r
- * This procedure performs following operations :\r
- * - Disable SPI Interrupts (depending of transfer direction)\r
- * - Disable the DMA transfer in the peripheral register (if enabled)\r
- * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r
- * - Set handle State to READY\r
- * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\r
-{\r
- HAL_StatusTypeDef errorcode;\r
- __IO uint32_t count, resetcount;\r
-\r
- /* Initialized local variable */\r
- errorcode = HAL_OK;\r
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
- count = resetcount;\r
-\r
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
-\r
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
- {\r
- hspi->TxISR = SPI_AbortTx_ISR;\r
- /* Wait HAL_SPI_STATE_ABORT state */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (hspi->State != HAL_SPI_STATE_ABORT);\r
- /* Reset Timeout Counter */\r
- count = resetcount;\r
- }\r
-\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
- {\r
- hspi->RxISR = SPI_AbortRx_ISR;\r
- /* Wait HAL_SPI_STATE_ABORT state */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (hspi->State != HAL_SPI_STATE_ABORT);\r
- /* Reset Timeout Counter */\r
- count = resetcount;\r
- }\r
-\r
- /* Disable the SPI DMA Tx request if enabled */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
- {\r
- /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- /* Set the SPI DMA Abort callback :\r
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
- /* Abort DMA Tx Handle linked to SPI Peripheral */\r
- if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable Tx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\r
-\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable SPI Peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
- }\r
- }\r
-\r
- /* Disable the SPI DMA Rx request if enabled */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
- {\r
- /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- /* Set the SPI DMA Abort callback :\r
- will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
- /* Abort DMA Rx Handle linked to SPI Peripheral */\r
- if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable Rx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\r
- }\r
- }\r
- /* Reset Tx and Rx transfer counters */\r
- hspi->RxXferCount = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Check error during Abort procedure */\r
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
- {\r
- /* return HAL_Error in case of error during Abort procedure */\r
- errorcode = HAL_ERROR;\r
- }\r
- else\r
- {\r
- /* Reset errorCode */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- }\r
-\r
- /* Clear the Error flags in the SR register */\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
- /* Restore hspi->state to ready */\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Abort ongoing transfer (Interrupt mode).\r
- * @param hspi SPI handle.\r
- * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r
- * started in Interrupt or DMA mode.\r
- * This procedure performs following operations :\r
- * - Disable SPI Interrupts (depending of transfer direction)\r
- * - Disable the DMA transfer in the peripheral register (if enabled)\r
- * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r
- * - Set handle State to READY\r
- * - At abort completion, call user abort complete callback\r
- * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be\r
- * considered as completed only when user abort complete callback is executed (not when exiting function).\r
- * @retval HAL status\r
-*/\r
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\r
-{\r
- HAL_StatusTypeDef errorcode;\r
- uint32_t abortcplt ;\r
- __IO uint32_t count, resetcount;\r
-\r
- /* Initialized local variable */\r
- errorcode = HAL_OK;\r
- abortcplt = 1U;\r
- resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
- count = resetcount;\r
-\r
- /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r
-\r
- /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r
- {\r
- hspi->TxISR = SPI_AbortTx_ISR;\r
- /* Wait HAL_SPI_STATE_ABORT state */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (hspi->State != HAL_SPI_STATE_ABORT);\r
- /* Reset Timeout Counter */\r
- count = resetcount;\r
- }\r
-\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
- {\r
- hspi->RxISR = SPI_AbortRx_ISR;\r
- /* Wait HAL_SPI_STATE_ABORT state */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (hspi->State != HAL_SPI_STATE_ABORT);\r
- /* Reset Timeout Counter */\r
- count = resetcount;\r
- }\r
-\r
- /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised\r
- before any call to DMA Abort functions */\r
- /* DMA Tx Handle is valid */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r
- Otherwise, set it to NULL */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
- {\r
- hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\r
- }\r
- else\r
- {\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
- }\r
- }\r
- /* DMA Rx Handle is valid */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r
- Otherwise, set it to NULL */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
- {\r
- hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\r
- }\r
- else\r
- {\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
- }\r
- }\r
-\r
- /* Disable the SPI DMA Tx request if enabled */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r
- {\r
- /* Abort the SPI DMA Tx Stream/Channel */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- /* Abort DMA Tx Handle linked to SPI Peripheral */\r
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r
- {\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
- else\r
- {\r
- abortcplt = 0U;\r
- }\r
- }\r
- }\r
- /* Disable the SPI DMA Rx request if enabled */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r
- {\r
- /* Abort the SPI DMA Rx Stream/Channel */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- /* Abort DMA Rx Handle linked to SPI Peripheral */\r
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)\r
- {\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
- else\r
- {\r
- abortcplt = 0U;\r
- }\r
- }\r
- }\r
-\r
- if (abortcplt == 1U)\r
- {\r
- /* Reset Tx and Rx transfer counters */\r
- hspi->RxXferCount = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Check error during Abort procedure */\r
- if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r
- {\r
- /* return HAL_Error in case of error during Abort procedure */\r
- errorcode = HAL_ERROR;\r
- }\r
- else\r
- {\r
- /* Reset errorCode */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- }\r
-\r
- /* Clear the Error flags in the SR register */\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
- /* Restore hspi->State to Ready */\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- /* As no DMA to be aborted, call directly user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->AbortCpltCallback(hspi);\r
-#else\r
- HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
-\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Pause the DMA Transfer.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI module.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Disable the SPI DMA Tx & Rx requests */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Resume the DMA Transfer.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI module.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Process Locked */\r
- __HAL_LOCK(hspi);\r
-\r
- /* Enable the SPI DMA Tx & Rx requests */\r
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Stop the DMA Transfer.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI module.\r
- * @retval HAL status\r
- */\r
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r
-{\r
- HAL_StatusTypeDef errorcode = HAL_OK;\r
- /* The Lock is not implemented on this API to allow the user application\r
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r
- */\r
-\r
- /* Abort the SPI DMA tx Stream/Channel */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
- }\r
- }\r
- /* Abort the SPI DMA rx Stream/Channel */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- errorcode = HAL_ERROR;\r
- }\r
- }\r
-\r
- /* Disable the SPI DMA Tx & Rx requests */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
- hspi->State = HAL_SPI_STATE_READY;\r
- return errorcode;\r
-}\r
-\r
-/**\r
- * @brief Handle SPI interrupt request.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for the specified SPI module.\r
- * @retval None\r
- */\r
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r
-{\r
- uint32_t itsource = hspi->Instance->CR2;\r
- uint32_t itflag = hspi->Instance->SR;\r
-\r
- /* SPI in mode Receiver ----------------------------------------------------*/\r
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&\r
- (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))\r
- {\r
- hspi->RxISR(hspi);\r
- return;\r
- }\r
-\r
- /* SPI in mode Transmitter -------------------------------------------------*/\r
- if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))\r
- {\r
- hspi->TxISR(hspi);\r
- return;\r
- }\r
-\r
- /* SPI in Error Treatment --------------------------------------------------*/\r
- if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))\r
- {\r
- /* SPI Overrun error interrupt occurred ----------------------------------*/\r
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)\r
- {\r
- if (hspi->State != HAL_SPI_STATE_BUSY_TX)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- }\r
- else\r
- {\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- return;\r
- }\r
- }\r
-\r
- /* SPI Mode Fault error interrupt occurred -------------------------------*/\r
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\r
- __HAL_SPI_CLEAR_MODFFLAG(hspi);\r
- }\r
-\r
- /* SPI Frame error interrupt occurred ------------------------------------*/\r
- if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\r
- __HAL_SPI_CLEAR_FREFLAG(hspi);\r
- }\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- /* Disable all interrupts */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Disable the SPI DMA requests if enabled */\r
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\r
- {\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r
-\r
- /* Abort the SPI DMA Rx channel */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- /* Set the SPI DMA Abort callback :\r
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- }\r
- }\r
- /* Abort the SPI DMA Tx channel */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- /* Set the SPI DMA Abort callback :\r
- will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r
- if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- }\r
- return;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Tx Transfer completed callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_TxCpltCallback should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Rx Transfer completed callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_RxCpltCallback should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Tx and Rx Transfer completed callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Tx Half Transfer completed callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Rx Half Transfer completed callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief Tx and Rx Half Transfer callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r
- */\r
-}\r
-\r
-/**\r
- * @brief SPI error callback.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_ErrorCallback should be implemented in the user file\r
- */\r
- /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r
- and user can use HAL_SPI_GetError() API to check the latest error occurred\r
- */\r
-}\r
-\r
-/**\r
- * @brief SPI Abort Complete callback.\r
- * @param hspi SPI handle.\r
- * @retval None\r
- */\r
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Prevent unused argument(s) compilation warning */\r
- UNUSED(hspi);\r
-\r
- /* NOTE : This function should not be modified, when the callback is needed,\r
- the HAL_SPI_AbortCpltCallback can be implemented in the user file.\r
- */\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r
- * @brief SPI control functions\r
- *\r
-@verbatim\r
- ===============================================================================\r
- ##### Peripheral State and Errors functions #####\r
- ===============================================================================\r
- [..]\r
- This subsection provides a set of functions allowing to control the SPI.\r
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r
- (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r
-@endverbatim\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Return the SPI handle state.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval SPI state\r
- */\r
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Return SPI handle state */\r
- return hspi->State;\r
-}\r
-\r
-/**\r
- * @brief Return the SPI error code.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval SPI error code in bitmap format\r
- */\r
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Return SPI ErrorCode */\r
- return hspi->ErrorCode;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup SPI_Private_Functions\r
- * @brief Private functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief DMA SPI transmit process complete callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
- uint32_t tickstart;\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* DMA Normal Mode */\r
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
- {\r
- /* Disable ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
- /* Disable Tx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- }\r
-\r
- /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
- {\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- }\r
-\r
- hspi->TxXferCount = 0U;\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- return;\r
- }\r
- }\r
- /* Call user Tx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI receive process complete callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
- uint32_t tickstart;\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* DMA Normal Mode */\r
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
- {\r
- /* Disable ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* CRC handling */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Wait until RXNE flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- }\r
- /* Read CRC */\r
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r
- {\r
- /* Read 16bit CRC */\r
- READ_REG(hspi->Instance->DR);\r
- }\r
- else\r
- {\r
- /* Read 8bit CRC */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r
- {\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- }\r
- /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
- }\r
- }\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r
- }\r
-\r
- hspi->RxXferCount = 0U;\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- return;\r
- }\r
- }\r
- /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->RxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI transmit receive process complete callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
- uint32_t tickstart;\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* DMA Normal Mode */\r
- if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)\r
- {\r
- /* Disable ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* CRC handling */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r
- {\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,\r
- tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- }\r
- /* Read CRC to Flush DR and RXNE flag */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
- }\r
- else\r
- {\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- /* Error on the CRC reception */\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- }\r
- /* Read CRC to Flush DR and RXNE flag */\r
- READ_REG(hspi->Instance->DR);\r
- }\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- }\r
-\r
- /* Disable Rx/Tx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
- hspi->TxXferCount = 0U;\r
- hspi->RxXferCount = 0U;\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- return;\r
- }\r
- }\r
- /* Call user TxRx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxRxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxRxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI half transmit process complete callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- /* Call user Tx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxHalfCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI half receive process complete callback\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- /* Call user Rx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->RxHalfCpltCallback(hspi);\r
-#else\r
- HAL_SPI_RxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI half transmit receive process complete callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- /* Call user TxRx half complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxRxHalfCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxRxHalfCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI communication error callback.\r
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
- * the configuration information for the specified DMA module.\r
- * @retval None\r
- */\r
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- /* Stop the disable DMA transfer on SPI side */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r
-\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI communication abort callback, when initiated by HAL services on Error\r
- * (To be called at end of DMA Abort procedure following error occurrence).\r
- * @param hdma DMA handle.\r
- * @retval None\r
- */\r
-static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
- hspi->RxXferCount = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI Tx communication abort callback, when initiated by user\r
- * (To be called at end of DMA Tx Abort procedure following user abort request).\r
- * @note When this callback is executed, User Abort complete call back is called only if no\r
- * Abort still ongoing for Rx DMA Handle.\r
- * @param hdma DMA handle.\r
- * @retval None\r
- */\r
-static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- hspi->hdmatx->XferAbortCallback = NULL;\r
-\r
- /* Disable Tx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r
-\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable SPI Peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Check if an Abort process is still ongoing */\r
- if (hspi->hdmarx != NULL)\r
- {\r
- if (hspi->hdmarx->XferAbortCallback != NULL)\r
- {\r
- return;\r
- }\r
- }\r
-\r
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
- hspi->RxXferCount = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Check no error during Abort procedure */\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
- {\r
- /* Reset errorCode */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- }\r
-\r
- /* Clear the Error flags in the SR register */\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
- /* Restore hspi->State to Ready */\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- /* Call user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->AbortCpltCallback(hspi);\r
-#else\r
- HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief DMA SPI Rx communication abort callback, when initiated by user\r
- * (To be called at end of DMA Rx Abort procedure following user abort request).\r
- * @note When this callback is executed, User Abort complete call back is called only if no\r
- * Abort still ongoing for Tx DMA Handle.\r
- * @param hdma DMA handle.\r
- * @retval None\r
- */\r
-static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r
-{\r
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
-\r
- /* Disable SPI Peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- hspi->hdmarx->XferAbortCallback = NULL;\r
-\r
- /* Disable Rx DMA Request */\r
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Check if an Abort process is still ongoing */\r
- if (hspi->hdmatx != NULL)\r
- {\r
- if (hspi->hdmatx->XferAbortCallback != NULL)\r
- {\r
- return;\r
- }\r
- }\r
-\r
- /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r
- hspi->RxXferCount = 0U;\r
- hspi->TxXferCount = 0U;\r
-\r
- /* Check no error during Abort procedure */\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r
- {\r
- /* Reset errorCode */\r
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r
- }\r
-\r
- /* Clear the Error flags in the SR register */\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- __HAL_SPI_CLEAR_FREFLAG(hspi);\r
-\r
- /* Restore hspi->State to Ready */\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- /* Call user Abort complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->AbortCpltCallback(hspi);\r
-#else\r
- HAL_SPI_AbortCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
-}\r
-\r
-/**\r
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Receive data in packing mode */\r
- if (hspi->RxXferCount > 1U)\r
- {\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount -= 2U;\r
- if (hspi->RxXferCount == 1U)\r
- {\r
- /* Set RX Fifo threshold according the reception data length: 8bit */\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- }\r
- }\r
- /* Receive data in 8 Bit mode */\r
- else\r
- {\r
- *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);\r
- hspi->pRxBuffPtr++;\r
- hspi->RxXferCount--;\r
- }\r
-\r
- /* Check end of the reception */\r
- if (hspi->RxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Disable RXNE and ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- if (hspi->TxXferCount == 0U)\r
- {\r
- SPI_CloseRxTx_ISR(hspi);\r
- }\r
- }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
- * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Read 8bit CRC to flush Data Regsiter */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
- hspi->CRCSize--;\r
-\r
- /* Check end of the reception */\r
- if (hspi->CRCSize == 0U)\r
- {\r
- /* Disable RXNE and ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- if (hspi->TxXferCount == 0U)\r
- {\r
- SPI_CloseRxTx_ISR(hspi);\r
- }\r
- }\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
- * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Transmit data in packing Bit mode */\r
- if (hspi->TxXferCount >= 2U)\r
- {\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount -= 2U;\r
- }\r
- /* Transmit data in 8 Bit mode */\r
- else\r
- {\r
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr++;\r
- hspi->TxXferCount--;\r
- }\r
-\r
- /* Check the end of the transmission */\r
- if (hspi->TxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Set CRC Next Bit to send CRC */\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- /* Disable TXE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Disable TXE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-\r
- if (hspi->RxXferCount == 0U)\r
- {\r
- SPI_CloseRxTx_ISR(hspi);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Receive data in 16 Bit mode */\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount--;\r
-\r
- if (hspi->RxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Disable RXNE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
-\r
- if (hspi->TxXferCount == 0U)\r
- {\r
- SPI_CloseRxTx_ISR(hspi);\r
- }\r
- }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
- * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Read 16bit CRC to flush Data Regsiter */\r
- READ_REG(hspi->Instance->DR);\r
-\r
- /* Disable RXNE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r
-\r
- SPI_CloseRxTx_ISR(hspi);\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
- * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Transmit data in 16 Bit mode */\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
-\r
- /* Enable CRC Transmission */\r
- if (hspi->TxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Set CRC Next Bit to send CRC */\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- /* Disable TXE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- /* Disable TXE interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r
-\r
- if (hspi->RxXferCount == 0U)\r
- {\r
- SPI_CloseRxTx_ISR(hspi);\r
- }\r
- }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
- * @brief Manage the CRC 8-bit receive in Interrupt context.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Read 8bit CRC to flush Data Register */\r
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\r
-\r
- hspi->CRCSize--;\r
-\r
- if (hspi->CRCSize == 0U)\r
- {\r
- SPI_CloseRx_ISR(hspi);\r
- }\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
- * @brief Manage the receive 8-bit in Interrupt context.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);\r
- hspi->pRxBuffPtr++;\r
- hspi->RxXferCount--;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Enable CRC Transmission */\r
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
- {\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->RxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- hspi->RxISR = SPI_RxISR_8BITCRC;\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
- SPI_CloseRx_ISR(hspi);\r
- }\r
-}\r
-\r
-#if (USE_SPI_CRC != 0U)\r
-/**\r
- * @brief Manage the CRC 16-bit receive in Interrupt context.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Read 16bit CRC to flush Data Register */\r
- READ_REG(hspi->Instance->DR);\r
-\r
- /* Disable RXNE and ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- SPI_CloseRx_ISR(hspi);\r
-}\r
-#endif /* USE_SPI_CRC */\r
-\r
-/**\r
- * @brief Manage the 16-bit receive in Interrupt context.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\r
- hspi->pRxBuffPtr += sizeof(uint16_t);\r
- hspi->RxXferCount--;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Enable CRC Transmission */\r
- if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r
- {\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
-\r
- if (hspi->RxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- hspi->RxISR = SPI_RxISR_16BITCRC;\r
- return;\r
- }\r
-#endif /* USE_SPI_CRC */\r
- SPI_CloseRx_ISR(hspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Handle the data 8-bit transmit in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr++;\r
- hspi->TxXferCount--;\r
-\r
- if (hspi->TxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Enable CRC Transmission */\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
- SPI_CloseTx_ISR(hspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Handle the data 16-bit transmit in Interrupt mode.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r
-{\r
- /* Transmit data in 16 Bit mode */\r
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r
- hspi->pTxBuffPtr += sizeof(uint16_t);\r
- hspi->TxXferCount--;\r
-\r
- if (hspi->TxXferCount == 0U)\r
- {\r
-#if (USE_SPI_CRC != 0U)\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- /* Enable CRC Transmission */\r
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r
- }\r
-#endif /* USE_SPI_CRC */\r
- SPI_CloseTx_ISR(hspi);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Handle SPI Communication Timeout.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param Flag SPI flag to check\r
- * @param State flag state to check\r
- * @param Timeout Timeout duration\r
- * @param Tickstart tick start value\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\r
- uint32_t Timeout, uint32_t Tickstart)\r
-{\r
- while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)\r
- {\r
- if (Timeout != HAL_MAX_DELAY)\r
- {\r
- if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
- {\r
- /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
- on both master and slave sides in order to resynchronize the master\r
- and slave for their respective CRC calculation */\r
-\r
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
- {\r
- /* Disable SPI peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
- }\r
-\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
-\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Handle SPI FIFO Communication Timeout.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param Fifo Fifo to check\r
- * @param State Fifo state to check\r
- * @param Timeout Timeout duration\r
- * @param Tickstart tick start value\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r
- uint32_t Timeout, uint32_t Tickstart)\r
-{\r
- while ((hspi->Instance->SR & Fifo) != State)\r
- {\r
- if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r
- {\r
- /* Read 8bit CRC to flush Data Register */\r
- READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));\r
- }\r
-\r
- if (Timeout != HAL_MAX_DELAY)\r
- {\r
- if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))\r
- {\r
- /* Disable the SPI and reset the CRC: the CRC value should be cleared\r
- on both master and slave sides in order to resynchronize the master\r
- and slave for their respective CRC calculation */\r
-\r
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
- {\r
- /* Disable SPI peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
- }\r
-\r
- /* Reset CRC Calculation */\r
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r
- {\r
- SPI_RESET_CRC(hspi);\r
- }\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
- /* Process Unlocked */\r
- __HAL_UNLOCK(hspi);\r
-\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Handle the check of the RX transaction complete.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @param Timeout Timeout duration\r
- * @param Tickstart tick start value\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
- {\r
- /* Disable SPI peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
- }\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- return HAL_TIMEOUT;\r
- }\r
-\r
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r
- {\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- return HAL_TIMEOUT;\r
- }\r
- }\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Handle the check of the RXTX or TX transaction complete.\r
- * @param hspi SPI handle\r
- * @param Timeout Timeout duration\r
- * @param Tickstart tick start value\r
- * @retval HAL status\r
- */\r
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\r
-{\r
- /* Control if the TX fifo is empty */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- return HAL_TIMEOUT;\r
- }\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- return HAL_TIMEOUT;\r
- }\r
-\r
- /* Control if the RX fifo is empty */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- return HAL_TIMEOUT;\r
- }\r
-\r
- return HAL_OK;\r
-}\r
-\r
-/**\r
- * @brief Handle the end of the RXTX transaction.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
- uint32_t tickstart;\r
-\r
- /* Init tickstart for timeout managment*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Disable ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- }\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
- {\r
- hspi->State = HAL_SPI_STATE_READY;\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- else\r
- {\r
-#endif /* USE_SPI_CRC */\r
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
- {\r
- if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r
- {\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->RxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- else\r
- {\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Call user TxRx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxRxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxRxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- }\r
- else\r
- {\r
- hspi->State = HAL_SPI_STATE_READY;\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
-#if (USE_SPI_CRC != 0U)\r
- }\r
-#endif /* USE_SPI_CRC */\r
-}\r
-\r
-/**\r
- * @brief Handle the end of the RX transaction.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
- /* Disable RXNE and ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- }\r
- hspi->State = HAL_SPI_STATE_READY;\r
-\r
-#if (USE_SPI_CRC != 0U)\r
- /* Check if CRC error occurred */\r
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- else\r
- {\r
-#endif /* USE_SPI_CRC */\r
- if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r
- {\r
- /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->RxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_RxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- else\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
-#if (USE_SPI_CRC != 0U)\r
- }\r
-#endif /* USE_SPI_CRC */\r
-}\r
-\r
-/**\r
- * @brief Handle the end of the TX transaction.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
- uint32_t tickstart;\r
-\r
- /* Init tickstart for timeout management*/\r
- tickstart = HAL_GetTick();\r
-\r
- /* Disable TXE and ERR interrupt */\r
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r
-\r
- /* Check the end of the transaction */\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r
- }\r
-\r
- /* Clear overrun flag in 2 Lines communication mode because received is not read */\r
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r
- {\r
- __HAL_SPI_CLEAR_OVRFLAG(hspi);\r
- }\r
-\r
- hspi->State = HAL_SPI_STATE_READY;\r
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r
- {\r
- /* Call user error callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->ErrorCallback(hspi);\r
-#else\r
- HAL_SPI_ErrorCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
- else\r
- {\r
- /* Call user Rx complete callback */\r
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\r
- hspi->TxCpltCallback(hspi);\r
-#else\r
- HAL_SPI_TxCpltCallback(hspi);\r
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Handle abort a Rx transaction.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
- __IO uint32_t count;\r
-\r
- /* Disable SPI Peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-\r
- /* Disable RXNEIE interrupt */\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
-\r
- /* Check RXNEIE is disabled */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- hspi->State = HAL_SPI_STATE_ABORT;\r
-}\r
-\r
-/**\r
- * @brief Handle abort a Tx or Rx/Tx transaction.\r
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r
- * the configuration information for SPI module.\r
- * @retval None\r
- */\r
-static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\r
-{\r
- __IO uint32_t count;\r
-\r
- count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\r
-\r
- /* Disable TXEIE interrupt */\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));\r
-\r
- /* Check TXEIE is disabled */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));\r
-\r
- if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Disable SPI Peripheral */\r
- __HAL_SPI_DISABLE(hspi);\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */\r
- if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r
- {\r
- /* Disable RXNEIE interrupt */\r
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));\r
-\r
- /* Check RXNEIE is disabled */\r
- do\r
- {\r
- if (count == 0U)\r
- {\r
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\r
- break;\r
- }\r
- count--;\r
- }\r
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));\r
-\r
- /* Control the BSY flag */\r
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
-\r
- /* Empty the FRLVL fifo */\r
- if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r
- {\r
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r
- }\r
- }\r
- hspi->State = HAL_SPI_STATE_ABORT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#endif /* HAL_SPI_MODULE_ENABLED */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
projects / freertos / blobdiff