Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / libsrc / axipmon_v6_6 / src / xaxipmon_g.c

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c
new file mode 100644 (file)
index 0000000..b54becb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c
@@ -0,0 +1,127 @@
+\r
+/*******************************************************************\r
+*\r
+* CAUTION: This file is automatically generated by HSI.\r
+* Version: \r
+* DO NOT EDIT.\r
+*\r
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*\r
+*Permission is hereby granted, free of charge, to any person obtaining a copy\r
+*of this software and associated documentation files (the Software), to deal\r
+*in the Software without restriction, including without limitation the rights\r
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
+*copies of the Software, and to permit persons to whom the Software is\r
+*furnished to do so, subject to the following conditions:\r
+*\r
+*The above copyright notice and this permission notice shall be included in\r
+*all copies or substantial portions of the Software.\r
+* \r
+* Use of the Software is limited solely to applications:\r
+*(a) running on a Xilinx device, or\r
+*(b) that interact with a Xilinx device through a bus or interconnect.\r
+*\r
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+*\r
+*Except as contained in this notice, the name of the Xilinx shall not be used\r
+*in advertising or otherwise to promote the sale, use or other dealings in\r
+*this Software without prior written authorization from Xilinx.\r
+*\r
+\r
+* \r
+* Description: Driver configuration\r
+*\r
+*******************************************************************/\r
+\r
+#include "xparameters.h"\r
+#include "xaxipmon.h"\r
+\r
+/*\r
+* The configuration table for devices\r
+*/\r
+\r
+XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] =\r
+{\r
+       {\r
+               XPAR_PSU_APM_0_DEVICE_ID,\r
+               XPAR_PSU_APM_0_BASEADDR,\r
+               XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH,\r
+               XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH,\r
+               XPAR_PSU_APM_0_ENABLE_EVENT_COUNT,\r
+               XPAR_PSU_APM_0_NUM_MONITOR_SLOTS,\r
+               XPAR_PSU_APM_0_NUM_OF_COUNTERS,\r
+               XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT,\r
+               XPAR_PSU_APM_0_ENABLE_EVENT_LOG,\r
+               XPAR_PSU_APM_0_FIFO_AXIS_DEPTH,\r
+               XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH,\r
+               XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH,\r
+               XPAR_PSU_APM_0_METRIC_COUNT_SCALE,\r
+               XPAR_PSU_APM_0_ENABLE_ADVANCED,\r
+               XPAR_PSU_APM_0_ENABLE_PROFILE,\r
+               XPAR_PSU_APM_0_ENABLE_TRACE,\r
+               XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID\r
+       },\r
+       {\r
+               XPAR_PSU_APM_1_DEVICE_ID,\r
+               XPAR_PSU_APM_1_BASEADDR,\r
+               XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH,\r
+               XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH,\r
+               XPAR_PSU_APM_1_ENABLE_EVENT_COUNT,\r
+               XPAR_PSU_APM_1_NUM_MONITOR_SLOTS,\r
+               XPAR_PSU_APM_1_NUM_OF_COUNTERS,\r
+               XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT,\r
+               XPAR_PSU_APM_1_ENABLE_EVENT_LOG,\r
+               XPAR_PSU_APM_1_FIFO_AXIS_DEPTH,\r
+               XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH,\r
+               XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH,\r
+               XPAR_PSU_APM_1_METRIC_COUNT_SCALE,\r
+               XPAR_PSU_APM_1_ENABLE_ADVANCED,\r
+               XPAR_PSU_APM_1_ENABLE_PROFILE,\r
+               XPAR_PSU_APM_1_ENABLE_TRACE,\r
+               XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID\r
+       },\r
+       {\r
+               XPAR_PSU_APM_2_DEVICE_ID,\r
+               XPAR_PSU_APM_2_BASEADDR,\r
+               XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH,\r
+               XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH,\r
+               XPAR_PSU_APM_2_ENABLE_EVENT_COUNT,\r
+               XPAR_PSU_APM_2_NUM_MONITOR_SLOTS,\r
+               XPAR_PSU_APM_2_NUM_OF_COUNTERS,\r
+               XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT,\r
+               XPAR_PSU_APM_2_ENABLE_EVENT_LOG,\r
+               XPAR_PSU_APM_2_FIFO_AXIS_DEPTH,\r
+               XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH,\r
+               XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH,\r
+               XPAR_PSU_APM_2_METRIC_COUNT_SCALE,\r
+               XPAR_PSU_APM_2_ENABLE_ADVANCED,\r
+               XPAR_PSU_APM_2_ENABLE_PROFILE,\r
+               XPAR_PSU_APM_2_ENABLE_TRACE,\r
+               XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID\r
+       },\r
+       {\r
+               XPAR_PSU_APM_5_DEVICE_ID,\r
+               XPAR_PSU_APM_5_BASEADDR,\r
+               XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH,\r
+               XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH,\r
+               XPAR_PSU_APM_5_ENABLE_EVENT_COUNT,\r
+               XPAR_PSU_APM_5_NUM_MONITOR_SLOTS,\r
+               XPAR_PSU_APM_5_NUM_OF_COUNTERS,\r
+               XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT,\r
+               XPAR_PSU_APM_5_ENABLE_EVENT_LOG,\r
+               XPAR_PSU_APM_5_FIFO_AXIS_DEPTH,\r
+               XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH,\r
+               XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH,\r
+               XPAR_PSU_APM_5_METRIC_COUNT_SCALE,\r
+               XPAR_PSU_APM_5_ENABLE_ADVANCED,\r
+               XPAR_PSU_APM_5_ENABLE_PROFILE,\r
+               XPAR_PSU_APM_5_ENABLE_TRACE,\r
+               XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID\r
+       }\r
+};\r
+\r
+\r