Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / libsrc / canps_v3_2 / src / xcanps_g.c

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
index 4063a44eb70259e97f54f9d3c98f834b0b5a5981..0ed8cd17c0181df25f0b3f22a1f26ff71e940879 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
@@ -5,7 +5,7 @@
 * Version: \r
 * DO NOT EDIT.\r
 *\r
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*\r
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*\r
 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
 *of this software and associated documentation files (the Software), to deal\r
 *in the Software without restriction, including without limitation the rights\r
@@ -44,7 +44,7 @@
 * The configuration table for devices\r
 */\r
 \r
-XCanPs_Config XCanPs_ConfigTable[] =\r
+XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] =\r
 {\r
        {\r
                XPAR_PSU_CAN_1_DEVICE_ID,\r