Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / libsrc / uartps_v3_1 / src / xuartps_g.c

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
deleted file mode 100644 (file)
index 94aaf5b..0000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ /dev/null
@@ -1,63 +0,0 @@
-\r
-/*******************************************************************\r
-*\r
-* CAUTION: This file is automatically generated by HSI.\r
-* Version: \r
-* DO NOT EDIT.\r
-*\r
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*\r
-*Permission is hereby granted, free of charge, to any person obtaining a copy\r
-*of this software and associated documentation files (the Software), to deal\r
-*in the Software without restriction, including without limitation the rights\r
-*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-*copies of the Software, and to permit persons to whom the Software is\r
-*furnished to do so, subject to the following conditions:\r
-*\r
-*The above copyright notice and this permission notice shall be included in\r
-*all copies or substantial portions of the Software.\r
-* \r
-* Use of the Software is limited solely to applications:\r
-*(a) running on a Xilinx device, or\r
-*(b) that interact with a Xilinx device through a bus or interconnect.\r
-*\r
-*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL \r
-*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\r
-*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT\r
-*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
-*\r
-*Except as contained in this notice, the name of the Xilinx shall not be used\r
-*in advertising or otherwise to promote the sale, use or other dealings in\r
-*this Software without prior written authorization from Xilinx.\r
-*\r
-\r
-* \r
-* Description: Driver configuration\r
-*\r
-*******************************************************************/\r
-\r
-#include "xparameters.h"\r
-#include "xuartps.h"\r
-\r
-/*\r
-* The configuration table for devices\r
-*/\r
-\r
-XUartPs_Config XUartPs_ConfigTable[] =\r
-{\r
-       {\r
-               XPAR_PSU_UART_0_DEVICE_ID,\r
-               XPAR_PSU_UART_0_BASEADDR,\r
-               XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,\r
-               XPAR_PSU_UART_0_HAS_MODEM\r
-       },\r
-       {\r
-               XPAR_PSU_UART_1_DEVICE_ID,\r
-               XPAR_PSU_UART_1_BASEADDR,\r
-               XPAR_PSU_UART_1_UART_CLK_FREQ_HZ,\r
-               XPAR_PSU_UART_1_HAS_MODEM\r
-       }\r
-};\r
-\r
-\r