Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the...

[freertos] / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / RTOSDemo_R5_bsp / psu_cortexr5_0 / libsrc / wdtps_v3_0 / src / xwdtps_g.c

diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 6ea6b192b9110c5cef30fe92e079439298aa37ad..94d8c47333f03b86e60735e5588519510096f3b2 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
 * Version: \r
 * DO NOT EDIT.\r
 *\r
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*\r
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*\r
 *Permission is hereby granted, free of charge, to any person obtaining a copy\r
 *of this software and associated documentation files (the Software), to deal\r
 *in the Software without restriction, including without limitation the rights\r
@@ -44,8 +44,12 @@
 * The configuration table for devices\r
 */\r
 \r
-XWdtPs_Config XWdtPs_ConfigTable[] =\r
+XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES] =\r
 {\r
+       {\r
+               XPAR_PSU_CSU_WDT_DEVICE_ID,\r
+               XPAR_PSU_CSU_WDT_BASEADDR\r
+       },\r
        {\r
                XPAR_PSU_WDT_0_DEVICE_ID,\r
                XPAR_PSU_WDT_0_BASEADDR\r