/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-#include <p32xxxx.h>\r
+ * FreeRTOS Kernel V10.0.1\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#include <xc.h>\r
#include <sys/asm.h>\r
\r
.set nomips16\r
.global vRegTest1\r
.global vRegTest2\r
\r
+ .set noreorder\r
+ .set noat\r
+ .ent error_loop\r
+\r
+/* Reg test tasks call the error loop when they find an error. Sitting in the\r
+tight error loop prevents them incrementing their ulRegTestnCycles counter, and\r
+so allows the check softwate timer to know an error has been found. */\r
+error_loop:\r
+ b .\r
+ nop\r
+\r
+ .end error_loop\r
+\r
\r
.set noreorder\r
.set noat\r
.ent vRegTest1\r
\r
-/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */\r
-\r
vRegTest1:\r
+ /* Fill the registers with known values. */\r
addiu $1, $0, 0x11\r
addiu $2, $0, 0x12\r
addiu $3, $0, 0x13\r
+ /* $4 contains the address of the loop counter - don't mess with $4. */\r
addiu $5, $0, 0x15\r
addiu $6, $0, 0x16\r
addiu $7, $0, 0x17\r
addiu $19, $0, 0x119\r
addiu $20, $0, 0x120\r
addiu $21, $0, 0x121\r
- addiu $22, $0, 0x122\r
addiu $23, $0, 0x123\r
addiu $24, $0, 0x124\r
addiu $25, $0, 0x125\r
addiu $30, $0, 0x130\r
+ addiu $22, $0, 0x131\r
+ mthi $22\r
+ addiu $22, $0, 0x132\r
+ mtlo $22\r
+\r
+vRegTest1Loop:\r
+ /* Check each register maintains the value assigned to it for the lifetime\r
+ of the task. */\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $1, -0x11\r
+ beq $22, $0, .+16\r
+ nop\r
+ /* The register value was not that expected. Jump to the error loop so the\r
+ cycle counter stops incrementing. */\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $2, -0x12\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $3, -0x13\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $5, -0x15\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $6, -0x16\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $7, -0x17\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $8, -0x18\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $9, -0x19\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $10, -0x110\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
\r
- addiu $1, $1, -0x11\r
- beq $1, $0, .+12\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $11, -0x111\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $2, $2, -0x12\r
- beq $2, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $3, $3, -0x13\r
- beq $3, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $12, -0x112\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $5, $5, -0x15\r
- beq $5, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $6, $6, -0x16\r
- beq $6, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $13, -0x113\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $7, $7, -0x17\r
- beq $7, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $8, $8, -0x18\r
- beq $8, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $14, -0x114\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $9, $9, -0x19\r
- beq $9, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $10, $10, -0x110\r
- beq $10, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $15, -0x115\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $11, $11, -0x111\r
- beq $11, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $12, $12, -0x112\r
- beq $12, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $16, -0x116\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $17, -0x117\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $13, $13, -0x113\r
- beq $13, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $14, $14, -0x114\r
- beq $14, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $18, -0x118\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $15, $15, -0x115\r
- beq $15, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $16, $16, -0x116\r
- beq $16, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $19, -0x119\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $17, $17, -0x117\r
- beq $17, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $18, $18, -0x118\r
- beq $18, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $20, -0x120\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $19, $19, -0x119\r
- beq $19, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $20, $20, -0x120\r
- beq $20, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $21, -0x121\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $21, $21, -0x121\r
- beq $21, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $22, $22, -0x122\r
- beq $22, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $23, -0x123\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $23, $23, -0x123\r
- beq $23, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $24, $24, -0x124\r
- beq $24, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $24, -0x124\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $25, $25, -0x125\r
- beq $25, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $30, $30, -0x130\r
- beq $30, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $25, -0x125\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- jr $31\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $30, -0x130\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ mfhi $22\r
+ addiu $22, $22, -0x131\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ mflo $22, $ac1\r
+ addiu $22, $22, -0x132\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ /* No errors detected. Increment the loop count so the check timer knows\r
+ this task is still running without error, then loop back to do it all\r
+ again. The address of the loop counter is in $4. */\r
+ lw $22, 0( $4 )\r
+ addiu $22, $22, 0x01\r
+ sw $22, 0( $4 )\r
+ b vRegTest1Loop\r
nop\r
\r
.end vRegTest1\r
.ent vRegTest2\r
\r
vRegTest2:\r
+ addiu $1, $0, 0x21\r
+ addiu $2, $0, 0x22\r
+ addiu $3, $0, 0x23\r
+ /* $4 contains the address of the loop counter - don't mess with $4. */\r
+ addiu $5, $0, 0x25\r
+ addiu $6, $0, 0x26\r
+ addiu $7, $0, 0x27\r
+ addiu $8, $0, 0x28\r
+ addiu $9, $0, 0x29\r
+ addiu $10, $0, 0x210\r
+ addiu $11, $0, 0x211\r
+ addiu $12, $0, 0x212\r
+ addiu $13, $0, 0x213\r
+ addiu $14, $0, 0x214\r
+ addiu $15, $0, 0x215\r
+ addiu $16, $0, 0x216\r
+ addiu $17, $0, 0x217\r
+ addiu $18, $0, 0x218\r
+ addiu $19, $0, 0x219\r
+ addiu $20, $0, 0x220\r
+ addiu $21, $0, 0x221\r
+ addiu $23, $0, 0x223\r
+ addiu $24, $0, 0x224\r
+ addiu $25, $0, 0x225\r
+ addiu $30, $0, 0x230\r
+ addiu $22, $0, 0x231\r
+ mthi $22\r
+ addiu $22, $0, 0x232\r
+ mtlo $22\r
\r
- addiu $1, $0, 0x10\r
- addiu $2, $0, 0x20\r
- addiu $3, $0, 0x30\r
- addiu $5, $0, 0x50\r
- addiu $6, $0, 0x60\r
- addiu $7, $0, 0x70\r
- addiu $8, $0, 0x80\r
- addiu $9, $0, 0x90\r
- addiu $10, $0, 0x100\r
- addiu $11, $0, 0x110\r
- addiu $12, $0, 0x120\r
- addiu $13, $0, 0x130\r
- addiu $14, $0, 0x140\r
- addiu $15, $0, 0x150\r
- addiu $16, $0, 0x160\r
- addiu $17, $0, 0x170\r
- addiu $18, $0, 0x180\r
- addiu $19, $0, 0x190\r
- addiu $20, $0, 0x200\r
- addiu $21, $0, 0x210\r
- addiu $22, $0, 0x220\r
- addiu $23, $0, 0x230\r
- addiu $24, $0, 0x240\r
- addiu $25, $0, 0x250\r
- addiu $30, $0, 0x300\r
-\r
- addiu $1, $1, -0x10\r
- beq $1, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $2, $2, -0x20\r
- beq $2, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $3, $3, -0x30\r
- beq $3, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $5, $5, -0x50\r
- beq $5, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $6, $6, -0x60\r
- beq $6, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $7, $7, -0x70\r
- beq $7, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $8, $8, -0x80\r
- beq $8, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $9, $9, -0x90\r
- beq $9, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $10, $10, -0x100\r
- beq $10, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $11, $11, -0x110\r
- beq $11, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $12, $12, -0x120\r
- beq $12, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $13, $13, -0x130\r
- beq $13, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $14, $14, -0x140\r
- beq $14, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $15, $15, -0x150\r
- beq $15, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $16, $16, -0x160\r
- beq $16, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $17, $17, -0x170\r
- beq $17, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $18, $18, -0x180\r
- beq $18, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $19, $19, -0x190\r
- beq $19, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $20, $20, -0x200\r
- beq $20, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $21, $21, -0x210\r
- beq $21, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $22, $22, -0x220\r
- beq $22, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $23, $23, -0x230\r
- beq $23, $0, .+12\r
- nop\r
- sw $0, 0($4)\r
- addiu $24, $24, -0x240\r
- beq $24, $0, .+12\r
+vRegTest2Loop:\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $1, -0x21\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- addiu $25, $25, -0x250\r
- beq $25, $0, .+12\r
+ b error_loop\r
nop\r
- sw $0, 0($4)\r
- addiu $30, $30, -0x300\r
- beq $30, $0, .+12\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $2, -0x22\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $3, -0x23\r
+ beq $22, $0, .+16\r
nop\r
- sw $0, 0($4)\r
- jr $31\r
+ b error_loop\r
nop\r
\r
- .end vRegTest2\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $5, -0x25\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $6, -0x26\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $7, -0x27\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $8, -0x28\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $9, -0x29\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $10, -0x210\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $11, -0x211\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $12, -0x212\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $13, -0x213\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $14, -0x214\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $15, -0x215\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $16, -0x216\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $17, -0x217\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $18, -0x218\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $19, -0x219\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $20, -0x220\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $21, -0x221\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $23, -0x223\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $24, -0x224\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $25, -0x225\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ addiu $22, $0, 0x00\r
+ addiu $22, $30, -0x230\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ mfhi $22\r
+ addiu $22, $22, -0x231\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ mflo $22, $ac1\r
+ addiu $22, $22, -0x232\r
+ beq $22, $0, .+16\r
+ nop\r
+ b error_loop\r
+ nop\r
+\r
+ /* No errors detected. Increment the loop count so the check timer knows\r
+ this task is still running without error, then loop back to do it all\r
+ again. The address of the loop counter is in $4. */\r
+ lw $22, 0( $4 )\r
+ addiu $22, $22, 0x01\r
+ sw $22, 0( $4 )\r
+ b vRegTest2Loop\r
+ nop\r
+\r
+ .end vRegTest2\r
+\r
+\r
\r
projects / freertos / blobdiff