Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE...

[freertos] / FreeRTOS / Demo / RISC-V-Qemu-sifive_e-Eclipse-GCC / full_demo / RegTest.S

diff --git a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
index 8eef086e6e266336582269fcaaec7a8c5b904c4a..83b80c111406d9f5e212895267a7553fe55603aa 100644 (file)
--- a/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
@@ -38,7 +38,7 @@
  * main_full.c.\r
  */\r
 \r
-.align( 8 )\r
+.align( 4 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -145,15 +145,14 @@ reg1_loop:
 reg1_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-       ebreak\r
        jal reg1_error_loop\r
 \r
-.align( 16 )\r
+.align( 4 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
-.align( 8 )\r
+.align( 4 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -257,10 +256,9 @@ Reg2_loop:
 reg2_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
-       ebreak\r
        jal reg2_error_loop\r
 \r
-.align( 16 )\r
+.align( 4 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r