-#if 0\r
/*******************************************************************************\r
* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.\r
*\r
\r
#include "riscv_hal.h"\r
\r
+#include "FreeRTOS.h"\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
extern void Software_IRQHandler(void);\r
extern void Timer_IRQHandle( void );\r
\r
-/*------------------------------------------------------------------------------\r
- * Increment value for the mtimecmp register in order to achieve a system tick\r
- * interrupt as specified through the SysTick_Config() function.\r
- */\r
-static uint64_t g_systick_increment = 0U;\r
-\r
-/*------------------------------------------------------------------------------\r
- * Disable all interrupts.\r
- */\r
-void __disable_irq(void)\r
-{\r
- clear_csr(mstatus, MSTATUS_MPIE);\r
- clear_csr(mstatus, MSTATUS_MIE);\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- * Enabler all interrupts.\r
- */\r
-void __enable_irq(void)\r
-{\r
- set_csr(mstatus, MSTATUS_MIE);\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- * Configure the machine timer to generate an interrupt.\r
- */\r
-uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- uint32_t ret_val = ERROR;\r
-\r
- g_systick_increment = (uint64_t)(ticks) / RTC_PRESCALER;\r
-\r
- if (g_systick_increment > 0U)\r
- {\r
- uint32_t mhart_id = read_csr(mhartid);\r
-\r
- PRCI->MTIMECMP[mhart_id] = PRCI->MTIME + g_systick_increment;\r
-\r
- set_csr(mie, MIP_MTIP);\r
-\r
- __enable_irq();\r
-\r
- ret_val = SUCCESS;\r
- }\r
-\r
- return ret_val;\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- * RISC-V interrupt handler for machine timer interrupts.\r
- */\r
-volatile uint32_t ulTimerInterrupts = 0;\r
-extern void Timer_IRQHandler( void );\r
-static void handle_m_timer_interrupt(void)\r
-{\r
-// clear_csr(mie, MIP_MTIP);\r
-\r
- Timer_IRQHandler();\r
-\r
-// PRCI->MTIMECMP[read_csr(mhartid)] = PRCI->MTIME + g_systick_increment;\r
-\r
-// set_csr(mie, MIP_MTIP);\r
-}\r
-\r
/*------------------------------------------------------------------------------\r
* RISC-V interrupt handler for external interrupts.\r
*/\r
/*------------------------------------------------------------------------------\r
*\r
*/\r
-static void handle_m_ext_interrupt(void)\r
+void handle_m_ext_interrupt(void)\r
{\r
uint32_t int_num = PLIC_ClaimIRQ();\r
uint8_t disable = EXT_IRQ_KEEP_ENABLED;\r
}\r
}\r
\r
-static void handle_m_soft_interrupt(void)\r
-{\r
- Software_IRQHandler();\r
-\r
- /*Clear software interrupt*/\r
- PRCI->MSIP[0] = 0x00U;\r
-}\r
-\r
-/*------------------------------------------------------------------------------\r
- * Trap/Interrupt handler\r
- */\r
-#define ENV_CALL_FROM_M_MODE 11\r
-extern void vTaskSwitchContext( void );\r
-\r
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t mepc)\r
-{\r
- /*_RB_*/\r
- if( mcause == ENV_CALL_FROM_M_MODE )\r
- {\r
- vTaskSwitchContext();\r
-\r
- /* Ensure not to return to the instruction that generated the exception. */\r
- mepc += 4;\r
- } else\r
- /*end _RB_*/\r
- if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))\r
- {\r
- handle_m_ext_interrupt();\r
- }\r
- else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))\r
- {\r
- handle_m_timer_interrupt();\r
- }\r
- else if ( (mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))\r
- {\r
- handle_m_soft_interrupt();\r
- }\r
- else\r
- {\r
-#ifndef NDEBUG\r
- /*\r
- Arguments supplied to this function are mcause, mepc (exception PC) and stack pointer\r
- based onprivileged-isa specification\r
- mcause values and meanings are:\r
- 0 Instruction address misaligned (mtval/mbadaddr is the address)\r
- 1 Instruction access fault (mtval/mbadaddr is the address)\r
- 2 Illegal instruction (mtval/mbadaddr contains the offending instruction opcode)\r
- 3 Breakpoint\r
- 4 Load address misaligned (mtval/mbadaddr is the address)\r
- 5 Load address fault (mtval/mbadaddr is the address)\r
- 6 Store/AMO address fault (mtval/mbadaddr is the address)\r
- 7 Store/AMO access fault (mtval/mbadaddr is the address)\r
- 8 Environment call from U-mode\r
- 9 Environment call from S-mode\r
- A Environment call from M-mode\r
- B Instruction page fault\r
- C Load page fault (mtval/mbadaddr is the address)\r
- E Store page fault (mtval/mbadaddr is the address)\r
- */\r
-\r
- uintptr_t mip = read_csr(mip); /* interrupt pending */\r
- uintptr_t mbadaddr = read_csr(mbadaddr); /* additional info and meaning depends on mcause */\r
- uintptr_t mtvec = read_csr(mtvec); /* trap vector */\r
- uintptr_t mscratch = read_csr(mscratch); /* temporary, sometimes might hold temporary value of a0 */\r
- uintptr_t mstatus = read_csr(mstatus); /* status contains many smaller fields: */\r
-\r
- /* breakpoint*/\r
- __asm("ebreak");\r
-#else\r
- _exit(1 + mcause);\r
-#endif\r
- }\r
- return mepc;\r
-}\r
\r
#ifdef __cplusplus\r
}\r
#endif\r
-#endif\r
projects / freertos / blobdiff