Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDR...

[freertos] / FreeRTOS / Demo / RISC-V_RV32_SiFive_HiFive1-RevB_IAR / settings / RTOSDemo.dnx

diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.dnx b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.dnx
index 1f16e8434ea1299abcad25b101d2a97dbb9cfdf8..153749553cda1ced929006b7f25bae6fa4b9da5b 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.dnx
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.dnx
@@ -12,7 +12,7 @@
         <ByteLimit>50</ByteLimit>\r
     </Stack>\r
     <DebugChecksum>\r
-        <Checksum>2321671989</Checksum>\r
+        <Checksum>93930437</Checksum>\r
     </DebugChecksum>\r
     <Disassembly>\r
         <InstrCount>0</InstrCount>\r
@@ -41,7 +41,7 @@
     </Jet>\r
     <PlDriver>\r
         <FirstRun>0</FirstRun>\r
-        <MemConfigValue>C:\devtools\IAR Systems\Embedded Workbench 8.3\riscv\config\debugger\SiFive\hifive1.ddf</MemConfigValue>\r
+        <MemConfigValue>C:\devtools\IAR Systems\Embedded Workbench 8.4\riscv\config\debugger\SiFive\hifive1.ddf</MemConfigValue>\r
     </PlDriver>\r
     <RiscvDriver>\r
         <EnableCache>1</EnableCache>\r