RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work...

[freertos] / FreeRTOS / Demo / RISC-V_RV32_SiFive_HiFive1_GCC / bsp / metal.default.lds

diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/bsp/metal.default.lds b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/bsp/metal.default.lds
index a2830784111504a648bf959eaab93057fe03ff91..1d45a92664c4f5465340d18824959c0f699c8510 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/bsp/metal.default.lds
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/bsp/metal.default.lds
@@ -211,13 +211,14 @@ SECTIONS
        PROVIDE( end = . );
        PROVIDE( metal_segment_bss_target_end = . );
 
-
        .stack :
        {
-               PROVIDE(metal_segment_stack_begin = .);
-               . = __stack_size;
-               PROVIDE( _sp = . );
+               . = ALIGN(16);
+               metal_segment_stack_begin = .;
+               . += __stack_size;
+               _sp = .;
                PROVIDE(metal_segment_stack_end = .);
+               __freertos_irq_stack_top = .;
        } >ram AT>ram :ram