--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+ .extern ulRegTest1LoopCounter\r
+ .extern ulRegTest2LoopCounter\r
+\r
+ .global vRegTest1Implementation\r
+ .global vRegTest2Implementation\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The register check tasks are described in the comments at the top of\r
+ * main_full.c.\r
+ */\r
+\r
+vRegTest1Implementation:\r
+\r
+ /* Fill the core registers with known values. */\r
+ li x5, 0x5\r
+ li x6, 0x6\r
+ li x7, 0x7\r
+ li x8, 0x8\r
+ li x9, 0x9\r
+ li x10, 0xa\r
+ li x11, 0xb\r
+ li x12, 0xc\r
+ li x13, 0xd\r
+ li x14, 0xe\r
+ li x15, 0xf\r
+ li x16, 0x10\r
+ li x17, 0x11\r
+ li x18, 0x12\r
+ li x19, 0x13\r
+ li x20, 0x14\r
+ li x21, 0x15\r
+ li x22, 0x16\r
+ li x23, 0x17\r
+ li x24, 0x18\r
+ li x25, 0x19\r
+ li x26, 0x1a\r
+ li x27, 0x1b\r
+ li x28, 0x1c\r
+ li x29, 0x1d\r
+ li x30, 0x1e\r
+\r
+reg1_loop:\r
+\r
+ /* Check each register still contains the expected known value.\r
+ vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation\r
+ uses x5 as the temporary. */\r
+ li x31, 0x5\r
+ bne x31, x5, reg1_error_loop\r
+ li x31, 0x6\r
+ bne x31, x6, reg1_error_loop\r
+ li x31, 0x7\r
+ bne x31, x7, reg1_error_loop\r
+ li x31, 0x8\r
+ bne x31, x8, reg1_error_loop\r
+ li x31, 0x9\r
+ bne x31, x9, reg1_error_loop\r
+ li x31, 0xa\r
+ bne x31, x10, reg1_error_loop\r
+ li x31, 0xb\r
+ bne x31, x11, reg1_error_loop\r
+ li x31, 0xc\r
+ bne x31, x12, reg1_error_loop\r
+ li x31, 0xd\r
+ bne x31, x13, reg1_error_loop\r
+ li x31, 0xe\r
+ bne x31, x14, reg1_error_loop\r
+ li x31, 0xf\r
+ bne x31, x15, reg1_error_loop\r
+ li x31, 0x10\r
+ bne x31, x16, reg1_error_loop\r
+ li x31, 0x11\r
+ bne x31, x17, reg1_error_loop\r
+ li x31, 0x12\r
+ bne x31, x18, reg1_error_loop\r
+ li x31, 0x13\r
+ bne x31, x19, reg1_error_loop\r
+ li x31, 0x14\r
+ bne x31, x20, reg1_error_loop\r
+ li x31, 0x15\r
+ bne x31, x21, reg1_error_loop\r
+ li x31, 0x16\r
+ bne x31, x22, reg1_error_loop\r
+ li x31, 0x17\r
+ bne x31, x23, reg1_error_loop\r
+ li x31, 0x18\r
+ bne x31, x24, reg1_error_loop\r
+ li x31, 0x19\r
+ bne x31, x25, reg1_error_loop\r
+ li x31, 0x1a\r
+ bne x31, x26, reg1_error_loop\r
+ li x31, 0x1b\r
+ bne x31, x27, reg1_error_loop\r
+ li x31, 0x1c\r
+ bne x31, x28, reg1_error_loop\r
+ li x31, 0x1d\r
+ bne x31, x29, reg1_error_loop\r
+ li x31, 0x1e\r
+ bne x31, x30, reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ lw x31, ulRegTest1LoopCounterConst\r
+ lw x30, 0(x31)\r
+ addi x30, x30, 1\r
+ sw x30, 0(x31)\r
+\r
+ /* Restore clobbered register reading for next loop. */\r
+ li x30, 0x1e\r
+\r
+ /* Yield to increase code coverage. */\r
+ ecall\r
+\r
+ /* Start again. */\r
+ jal reg1_loop\r
+\r
+reg1_error_loop:\r
+ /* Jump here if a register contains an uxpected value. This stops the loop\r
+ counter being incremented so the check task knows an error was found. */\r
+ jal reg1_error_loop\r
+\r
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+vRegTest2Implementation:\r
+\r
+ /* Fill the core registers with known values. */\r
+ li x6, 0x61\r
+ li x7, 0x71\r
+ li x8, 0x81\r
+ li x9, 0x91\r
+ li x10, 0xa1\r
+ li x11, 0xb1\r
+ li x12, 0xc1\r
+ li x13, 0xd1\r
+ li x14, 0xe1\r
+ li x15, 0xf1\r
+ li x16, 0x20\r
+ li x17, 0x21\r
+ li x18, 0x22\r
+ li x19, 0x23\r
+ li x20, 0x24\r
+ li x21, 0x25\r
+ li x22, 0x26\r
+ li x23, 0x27\r
+ li x24, 0x28\r
+ li x25, 0x29\r
+ li x26, 0x2a\r
+ li x27, 0x2b\r
+ li x28, 0x2c\r
+ li x29, 0x2d\r
+ li x30, 0x2e\r
+ li x31, 0x2f\r
+\r
+Reg2_loop:\r
+\r
+ /* Check each register still contains the expected known value.\r
+ vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation\r
+ uses x31 as the temporary. */\r
+ li x5, 0x61\r
+ bne x5, x6, reg2_error_loop\r
+ li x5, 0x71\r
+ bne x5, x7, reg2_error_loop\r
+ li x5, 0x81\r
+ bne x5, x8, reg2_error_loop\r
+ li x5, 0x91\r
+ bne x5, x9, reg2_error_loop\r
+ li x5, 0xa1\r
+ bne x5, x10, reg2_error_loop\r
+ li x5, 0xb1\r
+ bne x5, x11, reg2_error_loop\r
+ li x5, 0xc1\r
+ bne x5, x12, reg2_error_loop\r
+ li x5, 0xd1\r
+ bne x5, x13, reg2_error_loop\r
+ li x5, 0xe1\r
+ bne x5, x14, reg2_error_loop\r
+ li x5, 0xf1\r
+ bne x5, x15, reg2_error_loop\r
+ li x5, 0x20\r
+ bne x5, x16, reg2_error_loop\r
+ li x5, 0x21\r
+ bne x5, x17, reg2_error_loop\r
+ li x5, 0x22\r
+ bne x5, x18, reg2_error_loop\r
+ li x5, 0x23\r
+ bne x5, x19, reg2_error_loop\r
+ li x5, 0x24\r
+ bne x5, x20, reg2_error_loop\r
+ li x5, 0x25\r
+ bne x5, x21, reg2_error_loop\r
+ li x5, 0x26\r
+ bne x5, x22, reg2_error_loop\r
+ li x5, 0x27\r
+ bne x5, x23, reg2_error_loop\r
+ li x5, 0x28\r
+ bne x5, x24, reg2_error_loop\r
+ li x5, 0x29\r
+ bne x5, x25, reg2_error_loop\r
+ li x5, 0x2a\r
+ bne x5, x26, reg2_error_loop\r
+ li x5, 0x2b\r
+ bne x5, x27, reg2_error_loop\r
+ li x5, 0x2c\r
+ bne x5, x28, reg2_error_loop\r
+ li x5, 0x2d\r
+ bne x5, x29, reg2_error_loop\r
+ li x5, 0x2e\r
+ bne x5, x30, reg2_error_loop\r
+ li x5, 0x2f\r
+ bne x5, x31, reg2_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ lw x5, ulRegTest2LoopCounterConst\r
+ lw x6, 0(x5)\r
+ addi x6, x6, 1\r
+ sw x6, 0(x5)\r
+\r
+ /* Restore clobbered register reading for next loop. */\r
+ li x6, 0x61\r
+\r
+ /* Start again. */\r
+ jal Reg2_loop\r
+\r
+reg2_error_loop:\r
+ /* Jump here if a register contains an uxpected value. This stops the loop\r
+ counter being incremented so the check task knows an error was found. */\r
+ jal reg2_error_loop\r
+\r
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
+\r
+\r
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