Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the...

[freertos] / FreeRTOS / Demo / RISC-V_Renode_Emulator_SoftConsole / full_demo / RegTest.S

diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
index 67d902a0cab58e607827d66bc1f059af39f2ebf8..f2602c430bfd980ba089898e01ca82a271711ca8 100644 (file)
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
@@ -38,6 +38,7 @@
  * main_full.c.\r
  */\r
 \r
+.align( 4 )\r
 vRegTest1Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -144,12 +145,15 @@ reg1_loop:
 reg1_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
+       ebreak\r
        jal reg1_error_loop\r
 \r
+.align( 4 )\r
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
+.align( 4 )\r
 vRegTest2Implementation:\r
 \r
        /* Fill the core registers with known values. */\r
@@ -253,8 +257,10 @@ Reg2_loop:
 reg2_error_loop:\r
        /* Jump here if a register contains an uxpected value.  This stops the loop\r
        counter being incremented so the check task knows an error was found. */\r
+       ebreak\r
        jal reg2_error_loop\r
 \r
+.align( 4 )\r
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter\r
 \r
 \r