Update version number in readiness for V10.3.0 release. Sync SVN with reviewed releas...

[freertos] / FreeRTOS / Demo / RX600_RX63N-RSK_Renesas / RTOSDemo / IntQueueTimer.c

diff --git a/FreeRTOS/Demo/RX600_RX63N-RSK_Renesas/RTOSDemo/IntQueueTimer.c b/FreeRTOS/Demo/RX600_RX63N-RSK_Renesas/RTOSDemo/IntQueueTimer.c
deleted file mode 100644 (file)
index 1e13a24..0000000
--- a/FreeRTOS/Demo/RX600_RX63N-RSK_Renesas/RTOSDemo/IntQueueTimer.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.1.0\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
- * the IntQueue standard demo task - namely the configuration of the timers\r
- * that generate the interrupts and the interrupt entry points.\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo includes. */\r
-#include "IntQueueTimer.h"\r
-#include "IntQueue.h"\r
-\r
-/* Hardware specifics. */\r
-#include "iodefine.h"\r
-\r
-#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_2_3_FREQUENCY ( 2001UL )\r
-\r
-void vInitialiseTimerForIntQueueTest( void )\r
-{\r
-       /* Ensure interrupts do not start until full configuration is complete. */\r
-       portENTER_CRITICAL();\r
-       {\r
-               /* Cascade two 8bit timer channels to generate the interrupts. \r
-               8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
-               utilised for this test. */\r
-\r
-               /* Enable the timers. */\r
-               SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
-               SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
-\r
-               /* Enable compare match A interrupt request. */\r
-               TMR0.TCR.BIT.CMIEA = 1;\r
-               TMR2.TCR.BIT.CMIEA = 1;\r
-\r
-               /* Clear the timer on compare match A. */\r
-               TMR0.TCR.BIT.CCLR = 1;\r
-               TMR2.TCR.BIT.CCLR = 1;\r
-\r
-               /* Set the compare match value. */\r
-               TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
-               TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
-\r
-               /* 16 bit operation ( count from timer 1,2 ). */\r
-               TMR0.TCCR.BIT.CSS = 3;\r
-               TMR2.TCCR.BIT.CSS = 3;\r
-       \r
-               /* Use PCLK as the input. */\r
-               TMR1.TCCR.BIT.CSS = 1;\r
-               TMR3.TCCR.BIT.CSS = 1;\r
-       \r
-               /* Divide PCLK by 8. */\r
-               TMR1.TCCR.BIT.CKS = 2;\r
-               TMR3.TCCR.BIT.CKS = 2;\r
-       \r
-               /* Enable TMR 0, 2 interrupts. */\r
-               IEN( TMR0, CMIA0 ) = 1;\r
-               IEN( TMR2, CMIA2 ) = 1;\r
-\r
-               /* Set the timer interrupts to be above the kernel.  The interrupts are\r
-               assigned different priorities so they nest with each other. */\r
-               IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
-               IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );\r
-       }\r
-       portEXIT_CRITICAL();\r
-       \r
-       /* Ensure the interrupts are clear as they are edge detected. */\r
-       IR( TMR0, CMIA0 ) = 0;\r
-       IR( TMR2, CMIA2 ) = 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )\r
-void vT0_1InterruptHandler( void )\r
-{\r
-       portYIELD_FROM_ISR( xFirstTimerHandler() );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )\r
-void vT2_3InterruptHandler( void )\r
-{\r
-       portYIELD_FROM_ISR( xSecondTimerHandler() );\r
-}\r
-\r
-\r
-\r
-\r