+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.1.0\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and to permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/* Hardware specific includes. */\r
-#include "platform.h"\r
-#include "r_ether.h"\r
-#include "phy.h"\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* uIP includes. */\r
-#include "net/uip.h"\r
-\r
-/* The time to wait between attempts to obtain a free buffer. */\r
-#define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )\r
-\r
-/* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving\r
-up on attempting to obtain a free buffer all together. */\r
-#define emacBUFFER_WAIT_ATTEMPTS ( 30 )\r
-\r
-/* The number of Rx descriptors. */\r
-#define emacNUM_RX_DESCRIPTORS 8\r
-\r
-/* The number of Tx descriptors. When using uIP there is not point in having\r
-more than two. */\r
-#define emacNUM_TX_BUFFERS 2\r
-\r
-/* The total number of EMAC buffers to allocate. */\r
-#define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )\r
-\r
-/* The time to wait for the Tx descriptor to become free. */\r
-#define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )\r
-\r
-/* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to\r
-become free. */\r
-#define emacTX_WAIT_ATTEMPTS ( 50 )\r
-\r
-/* Only Rx end and Tx end interrupts are used by this driver. */\r
-#define emacTX_END_INTERRUPT ( 1UL << 21UL )\r
-#define emacRX_END_INTERRUPT ( 1UL << 18UL )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The buffers and descriptors themselves. */\r
-#pragma section _RX_DESC\r
- volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];\r
-#pragma section _TX_DESC\r
- volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];\r
-#pragma section _ETHERNET_BUFFERS\r
- struct\r
- {\r
- unsigned long ulAlignmentVariable;\r
- char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];\r
- } xEthernetBuffers;\r
-#pragma section\r
-\r
-\r
-\r
-\r
-/* Used to indicate which buffers are free and which are in use. If an index\r
-contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise \r
-the buffer is in use or about to be used. */\r
-static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Initialise both the Rx and Tx descriptors.\r
- */\r
-static void prvInitialiseDescriptors( void );\r
-\r
-/*\r
- * Return a pointer to a free buffer within xEthernetBuffers.\r
- */\r
-static unsigned char *prvGetNextBuffer( void );\r
-\r
-/*\r
- * Return a buffer to the list of free buffers.\r
- */\r
-static void prvReturnBuffer( unsigned char *pucBuffer );\r
-\r
-/*\r
- * Examine the status of the next Rx FIFO to see if it contains new data.\r
- */\r
-static unsigned long prvCheckRxFifoStatus( void );\r
-\r
-/*\r
- * Setup the microcontroller for communication with the PHY.\r
- */\r
-static void prvResetMAC( void );\r
-\r
-/*\r
- * Configure the Ethernet interface peripherals.\r
- */\r
-static void prvConfigureEtherCAndEDMAC( void );\r
-\r
-/*\r
- * Something has gone wrong with the descriptor usage. Reset all the buffers\r
- * and descriptors.\r
- */\r
-static void prvResetEverything( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Points to the Rx descriptor currently in use. */\r
-static ethfifo *pxCurrentRxDesc = NULL;\r
-\r
-/* The buffer used by the uIP stack to both receive and send. This points to\r
-one of the Ethernet buffers when its actually in use. */\r
-unsigned char *uip_buf = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vInitEmac( void )\r
-{\r
- /* Software reset. */\r
- prvResetMAC();\r
- \r
- /* Set the Rx and Tx descriptors into their initial state. */\r
- prvInitialiseDescriptors();\r
-\r
- /* Set the MAC address into the ETHERC */\r
- ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) | \r
- ( ( unsigned long ) configMAC_ADDR1 << 16UL ) | \r
- ( ( unsigned long ) configMAC_ADDR2 << 8UL ) | \r
- ( unsigned long ) configMAC_ADDR3;\r
- \r
- ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |\r
- ( unsigned long ) configMAC_ADDR5;\r
-\r
- /* Perform rest of interface hardware configuration. */\r
- prvConfigureEtherCAndEDMAC();\r
- \r
- /* Nothing received yet, so uip_buf points nowhere. */\r
- uip_buf = NULL;\r
-\r
- /* Initialize the PHY */\r
- phy_init();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vEMACWrite( void )\r
-{\r
-long x;\r
-\r
- /* Wait until the second transmission of the last packet has completed. */\r
- for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )\r
- {\r
- if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )\r
- {\r
- /* Descriptor is still active. */\r
- vTaskDelay( emacTX_WAIT_DELAY_ms );\r
- }\r
- else\r
- {\r
- break;\r
- }\r
- }\r
- \r
- /* Is the descriptor free after waiting for it? */\r
- if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )\r
- {\r
- /* Something has gone wrong. */\r
- prvResetEverything();\r
- }\r
- \r
- /* Setup both descriptors to transmit the frame. */\r
- xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;\r
- xTxDescriptors[ 0 ].bufsize = uip_len; \r
- xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;\r
- xTxDescriptors[ 1 ].bufsize = uip_len;\r
-\r
- /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer\r
- for use by the stack. */\r
- uip_buf = prvGetNextBuffer();\r
-\r
- /* Clear previous settings and go. */\r
- xTxDescriptors[0].status &= ~( FP1 | FP0 );\r
- xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );\r
- xTxDescriptors[1].status &= ~( FP1 | FP0 );\r
- xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );\r
-\r
- EDMAC.EDTRR.LONG = 0x00000001;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-unsigned long ulEMACRead( void )\r
-{\r
-unsigned long ulBytesReceived;\r
-\r
- ulBytesReceived = prvCheckRxFifoStatus();\r
-\r
- if( ulBytesReceived > 0 )\r
- {\r
- /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to\r
- the buffer that contains the received data. */\r
- prvReturnBuffer( uip_buf );\r
-\r
- /* Point uip_buf to the data about ot be processed. */\r
- uip_buf = ( void * ) pxCurrentRxDesc->buf_p;\r
- \r
- /* Allocate a new buffer to the descriptor, as uip_buf is now using it's\r
- old descriptor. */\r
- pxCurrentRxDesc->buf_p = prvGetNextBuffer();\r
-\r
- /* Prepare the descriptor to go again. */\r
- pxCurrentRxDesc->status &= ~( FP1 | FP0 );\r
- pxCurrentRxDesc->status |= ACT;\r
-\r
- /* Move onto the next buffer in the ring. */\r
- pxCurrentRxDesc = pxCurrentRxDesc->next;\r
- \r
- if( EDMAC.EDRRR.LONG == 0x00000000L )\r
- {\r
- /* Restart Ethernet if it has stopped */\r
- EDMAC.EDRRR.LONG = 0x00000001L;\r
- }\r
- }\r
-\r
- return ulBytesReceived;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-long lEMACWaitForLink( void )\r
-{\r
-long lReturn;\r
-\r
- /* Set the link status. */\r
- switch( phy_set_autonegotiate() )\r
- {\r
- /* Half duplex link */\r
- case PHY_LINK_100H:\r
- ETHERC.ECMR.BIT.DM = 0;\r
- ETHERC.ECMR.BIT.RTM = 1;\r
- lReturn = pdPASS;\r
- break;\r
-\r
- case PHY_LINK_10H:\r
- ETHERC.ECMR.BIT.DM = 0;\r
- ETHERC.ECMR.BIT.RTM = 0;\r
- lReturn = pdPASS;\r
- break;\r
-\r
-\r
- /* Full duplex link */\r
- case PHY_LINK_100F:\r
- ETHERC.ECMR.BIT.DM = 1;\r
- ETHERC.ECMR.BIT.RTM = 1;\r
- lReturn = pdPASS;\r
- break;\r
- \r
- case PHY_LINK_10F:\r
- ETHERC.ECMR.BIT.DM = 1;\r
- ETHERC.ECMR.BIT.RTM = 0;\r
- lReturn = pdPASS;\r
- break;\r
-\r
- default:\r
- lReturn = pdFAIL;\r
- break;\r
- }\r
-\r
- if( lReturn == pdPASS )\r
- {\r
- /* Enable receive and transmit. */\r
- ETHERC.ECMR.BIT.RE = 1;\r
- ETHERC.ECMR.BIT.TE = 1;\r
-\r
- /* Enable EDMAC receive */\r
- EDMAC.EDRRR.LONG = 0x1;\r
- }\r
- \r
- return lReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvInitialiseDescriptors( void )\r
-{\r
-ethfifo *pxDescriptor;\r
-long x;\r
-\r
- for( x = 0; x < emacNUM_BUFFERS; x++ )\r
- {\r
- /* Ensure none of the buffers are shown as in use at the start. */\r
- ucBufferInUse[ x ] = pdFALSE;\r
- }\r
-\r
- /* Initialise the Rx descriptors. */\r
- for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )\r
- {\r
- pxDescriptor = &( xRxDescriptors[ x ] );\r
- pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );\r
-\r
- pxDescriptor->bufsize = UIP_BUFSIZE;\r
- pxDescriptor->size = 0;\r
- pxDescriptor->status = ACT;\r
- pxDescriptor->next = &xRxDescriptors[ x + 1 ]; \r
- \r
- /* Mark this buffer as in use. */\r
- ucBufferInUse[ x ] = pdTRUE;\r
- }\r
-\r
- /* The last descriptor points back to the start. */\r
- pxDescriptor->status |= DL;\r
- pxDescriptor->next = &xRxDescriptors[ 0 ];\r
- \r
- /* Initialise the Tx descriptors. */\r
- for( x = 0; x < emacNUM_TX_BUFFERS; x++ )\r
- {\r
- pxDescriptor = &( xTxDescriptors[ x ] );\r
- \r
- /* A buffer is not allocated to the Tx descriptor until a send is\r
- actually required. */\r
- pxDescriptor->buf_p = NULL;\r
-\r
- pxDescriptor->bufsize = UIP_BUFSIZE;\r
- pxDescriptor->size = 0;\r
- pxDescriptor->status = 0;\r
- pxDescriptor->next = &xTxDescriptors[ x + 1 ]; \r
- }\r
-\r
- /* The last descriptor points back to the start. */\r
- pxDescriptor->status |= DL;\r
- pxDescriptor->next = &( xTxDescriptors[ 0 ] );\r
- \r
- /* Use the first Rx descriptor to start with. */\r
- pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static unsigned char *prvGetNextBuffer( void )\r
-{\r
-long x;\r
-unsigned char *pucReturn = NULL;\r
-unsigned long ulAttempts = 0;\r
-\r
- while( pucReturn == NULL )\r
- {\r
- /* Look through the buffers to find one that is not in use by\r
- anything else. */\r
- for( x = 0; x < emacNUM_BUFFERS; x++ )\r
- {\r
- if( ucBufferInUse[ x ] == pdFALSE )\r
- {\r
- ucBufferInUse[ x ] = pdTRUE;\r
- pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );\r
- break;\r
- }\r
- }\r
-\r
- /* Was a buffer found? */\r
- if( pucReturn == NULL )\r
- {\r
- ulAttempts++;\r
-\r
- if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )\r
- {\r
- break;\r
- }\r
-\r
- /* Wait then look again. */\r
- vTaskDelay( emacBUFFER_WAIT_DELAY_ms );\r
- }\r
- }\r
-\r
- return pucReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvReturnBuffer( unsigned char *pucBuffer )\r
-{\r
-unsigned long ul;\r
-\r
- /* Return a buffer to the pool of free buffers. */\r
- for( ul = 0; ul < emacNUM_BUFFERS; ul++ )\r
- {\r
- if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )\r
- {\r
- ucBufferInUse[ ul ] = pdFALSE;\r
- break;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvResetEverything( void )\r
-{\r
- /* Temporary code just to see if this gets called. This function has not\r
- been implemented. */\r
- portDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static unsigned long prvCheckRxFifoStatus( void )\r
-{\r
-unsigned long ulReturn = 0;\r
-\r
- if( ( pxCurrentRxDesc->status & ACT ) != 0 )\r
- {\r
- /* Current descriptor is still active. */\r
- }\r
- else if( ( pxCurrentRxDesc->status & FE ) != 0 )\r
- {\r
- /* Frame error. Clear the error. */\r
- pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );\r
- pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );\r
- pxCurrentRxDesc->status |= ACT;\r
- pxCurrentRxDesc = pxCurrentRxDesc->next;\r
-\r
- if( EDMAC.EDRRR.LONG == 0x00000000UL )\r
- {\r
- /* Restart Ethernet if it has stopped. */\r
- EDMAC.EDRRR.LONG = 0x00000001UL;\r
- } \r
- }\r
- else\r
- {\r
- /* The descriptor contains a frame. Because of the size of the buffers\r
- the frame should always be complete. */\r
- if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )\r
- {\r
- ulReturn = pxCurrentRxDesc->size;\r
- }\r
- else\r
- {\r
- /* Do not expect to get here. */\r
- prvResetEverything();\r
- }\r
- }\r
- \r
- return ulReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvResetMAC( void )\r
-{\r
- /* Ensure the EtherC and EDMAC are enabled. */\r
- SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;\r
- vTaskDelay( 100 / portTICK_PERIOD_MS );\r
- \r
- EDMAC.EDMR.BIT.SWR = 1; \r
- \r
- /* Crude wait for reset to complete. */\r
- vTaskDelay( 500 / portTICK_PERIOD_MS ); \r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvConfigureEtherCAndEDMAC( void )\r
-{\r
- /* Initialisation code taken from Renesas example project. */\r
- \r
- /* TODO: Check bit 5 */\r
- ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */\r
-\r
- /* Set the EDMAC interrupt priority. */\r
- _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
-\r
- /* TODO: Check bit 5 */\r
- /* Enable interrupts of interest only. */\r
- EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;\r
- ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */\r
- ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */\r
-\r
- /* EDMAC */\r
- EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */\r
- #ifdef __LIT\r
- EDMAC.EDMR.BIT.DE = 1;\r
- #endif\r
- EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */\r
- EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */\r
- EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */\r
- EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */\r
- EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */\r
- EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */\r
- ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */\r
- \r
- /* Enable the interrupt... */\r
- _IEN( _ETHER_EINT ) = 1; \r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )\r
-void vEMAC_ISR_Handler( void )\r
-{\r
-unsigned long ul = EDMAC.EESR.LONG;\r
-long lHigherPriorityTaskWoken = pdFALSE;\r
-extern QueueHandle_t xEMACEventQueue;\r
-const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;\r
-\r
- /* Has a Tx end occurred? */\r
- if( ul & emacTX_END_INTERRUPT )\r
- {\r
- /* Only return the buffer to the pool once both Txes have completed. */\r
- prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );\r
- EDMAC.EESR.LONG = emacTX_END_INTERRUPT;\r
- }\r
-\r
- /* Has an Rx end occurred? */\r
- if( ul & emacRX_END_INTERRUPT )\r
- {\r
- /* Make sure the Ethernet task is not blocked waiting for a packet. */\r
- xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );\r
- portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
- EDMAC.EESR.LONG = emacRX_END_INTERRUPT;\r
- }\r
-}\r
-\r
projects / freertos / blobdiff