/*\r
- FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd. \r
+ FreeRTOS V8.1.0 - Copyright (C) 2014 Real Time Engineers Ltd. \r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
*/\r
\r
/*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
+ * This file contains the non-portable and therefore RX64M specific parts of\r
* the IntQueue standard demo task - namely the configuration of the timers\r
* that generate the interrupts and the interrupt entry points.\r
*/\r
\r
/* Renesas includes. */\r
#include "r_cg_macrodriver.h"\r
+#include "RegisterWriteProtect.h"\r
\r
#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
#define tmrTIMER_2_3_FREQUENCY ( 2001UL )\r
\r
void vInitialiseTimerForIntQueueTest( void )\r
{\r
-#if 0\r
/* Ensure interrupts do not start until full configuration is complete. */\r
portENTER_CRITICAL();\r
{\r
+ EnablePRCR( PRC1_BIT );\r
+\r
/* Cascade two 8bit timer channels to generate the interrupts. \r
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
utilised for this test. */\r
/* Divide PCLK by 8. */\r
TMR1.TCCR.BIT.CKS = 2;\r
TMR3.TCCR.BIT.CKS = 2;\r
-#warning Need to enable and configure interrupts here.\r
- /* Enable TMR 0, 2 interrupts. */\r
-// IEN( TMR0, CMIA0 ) = 1;\r
-// IEN( TMR2, CMIA2 ) = 1;\r
-// CMT _IEN( _CMT0_CMI0 ) = 1;\r
-\r
- /* ...and set its priority to the application defined kernel priority. */\r
-// CMT _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
-\r
\r
+ /* Enable TMR 0, 2 interrupts. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
\r
- /* Set the timer interrupts to be above the kernel. The interrupts are\r
- assigned different priorities so they nest with each other. */\r
-// IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
-// IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );\r
+ /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set\r
+ priority above the kernel's priority, but below the max syscall\r
+ priority. */\r
+ ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */\r
+ IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IEN( PERIB, INTB128 ) = 1;\r
+\r
+ /* Ensure that the flag is set to 0, otherwise the interrupt will not be\r
+ accepted. */\r
+ IR( PERIB, INTB128 ) = 0;\r
+\r
+ /* Do the same for TMR2, but to vector 129. */\r
+ ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */\r
+ IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+ IEN( PERIB, INTB129 ) = 1;\r
+ IR( PERIB, INTB129 ) = 0;\r
}\r
portEXIT_CRITICAL();\r
- \r
- /* Ensure the interrupts are clear as they are edge detected. */\r
-// IR( TMR0, CMIA0 ) = 0;\r
-// IR( TMR2, CMIA2 ) = 0;\r
-#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
-//#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )\r
-// CMT#pragma interrupt (vT0_1InterruptHandler( vect = _VECT( _CMT0_CMI0 ), enable ) )\r
-void vT0_1InterruptHandler( void )\r
+#pragma interrupt ( Excep_PERIB_INTB128( vect = 128, enable ) )\r
+void Excep_PERIB_INTB128( void )\r
{\r
portYIELD_FROM_ISR( xFirstTimerHandler() );\r
}\r
/*-----------------------------------------------------------*/\r
\r
-//#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )\r
-void vT2_3InterruptHandler( void )\r
+#pragma interrupt ( Excep_PERIB_INTB129( vect = 129, enable ) )\r
+void Excep_PERIB_INTB129( void )\r
{\r
portYIELD_FROM_ISR( xSecondTimerHandler() );\r
}\r
projects / freertos / blobdiff