+ + RISC-V port updates: The machine timer compare register can now be for\r
+ any HART, and correct the sequence used to update the 64-bit machine timer\r
+ compare register on 32-bit cores.\r
+ + Update Keil projects that use the MPU so memory regions come from linker\r
+ script (scatter file) variables instead of being hard coded.\r
+ + Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler\r
+ ports.\r
+ + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to\r
+ match that of the ARMv8-M ports whereby privilege escalations can only\r
+ originate from within the kernel's own memory segment.\r
+ + Added LPC51U68 Cortex-M0+ port for GCC (MCUXpresso), Keil and IAR\r
+ compilers.\r
+ + Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo.\r
+ + Added xTaskAbortDelayFromISR() API function.\r
+ + Added xTaskNotifyValueClear() API function.\r