/*\r
- FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd. \r
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
All rights reserved\r
\r
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
the terms of the GNU General Public License (version 2) as published by the\r
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
\r
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
#include "AT91SAM7X256.h"\r
\r
/* Constants required to handle interrupts. */\r
-#define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )\r
-#define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )\r
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )\r
\r
/* Constants required to handle critical sections. */\r
-#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )\r
-volatile unsigned long ulCriticalNesting = 9999UL;\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
+volatile uint32_t ulCriticalNesting = 9999UL;\r
\r
/*-----------------------------------------------------------*/\r
\r
/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
\r
-/* \r
+/*\r
* The scheduler can only be started from ARM mode, hence the inclusion of this\r
* function here.\r
*/\r
/*\r
* Called by portYIELD() or taskYIELD() to manually force a context switch.\r
*\r
- * When a context switch is performed from the task level the saved task \r
+ * When a context switch is performed from the task level the saved task\r
* context is made to look as if it occurred from within the tick ISR. This\r
* way the same restore context function can be used when restoring the context\r
* saved from the ISR or that saved from a call to vPortYieldProcessor.\r
*/\r
void vPortYieldProcessor( void )\r
{\r
- /* Within an IRQ ISR the link register has an offset from the true return \r
- address, but an SWI ISR does not. Add the offset manually so the same \r
+ /* Within an IRQ ISR the link register has an offset from the true return\r
+ address, but an SWI ISR does not. Add the offset manually so the same\r
ISR return code can be used in both cases. */\r
- asm volatile ( "ADD LR, LR, #4" );\r
+ __asm volatile ( "ADD LR, LR, #4" );\r
\r
/* Perform the context switch. First save the context of the current task. */\r
portSAVE_CONTEXT();\r
vTaskSwitchContext();\r
\r
/* Restore the context of the new task. */\r
- portRESTORE_CONTEXT(); \r
+ portRESTORE_CONTEXT();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
+/*\r
* The ISR used for the scheduler tick depends on whether the cooperative or\r
* the preemptive scheduler is being used.\r
*/\r
\r
#if configUSE_PREEMPTION == 0\r
\r
- /* The cooperative scheduler requires a normal IRQ service routine to \r
+ /* The cooperative scheduler requires a normal IRQ service routine to\r
simply increment the system tick. */\r
void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));\r
void vNonPreemptiveTick( void )\r
- { \r
- unsigned long ulDummy;\r
- \r
+ {\r
+ uint32_t ulDummy;\r
+\r
/* Increment the tick count - which may wake some tasks but as the\r
preemptive scheduler is not being used any woken task is not given\r
processor time no matter what its priority. */\r
xTaskIncrementTick();\r
- \r
+\r
/* Clear the PIT interrupt. */\r
ulDummy = AT91C_BASE_PITC->PITC_PIVR;\r
- \r
+\r
/* End the interrupt in the AIC. */\r
AT91C_BASE_AIC->AIC_EOICR = ulDummy;\r
}\r
void vPreemptiveTick( void )\r
{\r
/* Save the context of the current task. */\r
- portSAVE_CONTEXT(); \r
+ portSAVE_CONTEXT();\r
\r
/* Increment the tick count - this may wake a task. */\r
if( xTaskIncrementTick() != pdFALSE )\r
/* Find the highest priority task that is ready to run. */\r
vTaskSwitchContext();\r
}\r
- \r
+\r
/* End the interrupt in the AIC. */\r
- AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;\r
- \r
+ AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;\r
+\r
portRESTORE_CONTEXT();\r
}\r
\r
\r
void vPortDisableInterruptsFromThumb( void )\r
{\r
- asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
- \r
+\r
void vPortEnableInterruptsFromThumb( void )\r
{\r
- asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
void vPortEnterCritical( void )\r
{\r
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
- asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
\r
- /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
directly. Increment ulCriticalNesting to keep a count of how many times\r
portENTER_CRITICAL() has been called. */\r
ulCriticalNesting++;\r
if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
{\r
/* Enable interrupts as per portEXIT_CRITICAL(). */\r
- asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
}\r
}\r
projects / freertos / blobdiff