/*\r
- FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
-\r
- >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- details. You should have received a copy of the GNU General Public License\r
- and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- writing to Real Time Engineers Ltd., contact details for whom are available\r
- on the FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- fully thread aware and reentrant UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
- indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
- mission critical applications that require provable dependability.\r
-*/\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
\r
/*-----------------------------------------------------------\r
\r
/*\r
Changes from V2.5.2\r
- \r
+\r
+ The critical section management functions have been changed. These no\r
longer modify the stack and are safe to use at all optimisation levels.\r
The functions are now also the same for both ARM and THUMB modes.\r
\r
Changes from V2.6.0\r
\r
- + Removed the 'static' from the definition of vNonPreemptiveTick() to \r
+ + Removed the 'static' from the definition of vNonPreemptiveTick() to\r
allow the demo to link when using the cooperative scheduler.\r
\r
Changes from V3.2.4\r
#include "FreeRTOS.h"\r
\r
/* Constants required to handle interrupts. */\r
-#define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )\r
-#define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )\r
+#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )\r
+#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )\r
\r
/* Constants required to handle critical sections. */\r
-#define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )\r
-volatile unsigned long ulCriticalNesting = 9999UL;\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
+volatile uint32_t ulCriticalNesting = 9999UL;\r
\r
/*-----------------------------------------------------------*/\r
\r
/* ISR to handle manual context switches (from a call to taskYIELD()). */\r
void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
\r
-/* \r
+/*\r
* The scheduler can only be started from ARM mode, hence the inclusion of this\r
* function here.\r
*/\r
/*\r
* Called by portYIELD() or taskYIELD() to manually force a context switch.\r
*\r
- * When a context switch is performed from the task level the saved task \r
+ * When a context switch is performed from the task level the saved task\r
* context is made to look as if it occurred from within the tick ISR. This\r
* way the same restore context function can be used when restoring the context\r
* saved from the ISR or that saved from a call to vPortYieldProcessor.\r
*/\r
void vPortYieldProcessor( void )\r
{\r
- /* Within an IRQ ISR the link register has an offset from the true return \r
- address, but an SWI ISR does not. Add the offset manually so the same \r
+ /* Within an IRQ ISR the link register has an offset from the true return\r
+ address, but an SWI ISR does not. Add the offset manually so the same\r
ISR return code can be used in both cases. */\r
__asm volatile ( "ADD LR, LR, #4" );\r
\r
__asm volatile ( "bl vTaskSwitchContext" );\r
\r
/* Restore the context of the new task. */\r
- portRESTORE_CONTEXT(); \r
+ portRESTORE_CONTEXT();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
+/*\r
* The ISR used for the scheduler tick.\r
*/\r
void vTickISR( void ) __attribute__((naked));\r
void vTickISR( void )\r
{\r
/* Save the context of the interrupted task. */\r
- portSAVE_CONTEXT(); \r
+ portSAVE_CONTEXT();\r
\r
- /* Increment the RTOS tick count, then look for the highest priority \r
+ /* Increment the RTOS tick count, then look for the highest priority\r
task that is ready to run. */\r
- __asm volatile( "bl xTaskIncrementTick" );\r
-\r
- #if configUSE_PREEMPTION == 1\r
- __asm volatile( "bl vTaskSwitchContext" );\r
- #endif\r
+ __asm volatile\r
+ (\r
+ " bl xTaskIncrementTick \t\n" \\r
+ " cmp r0, #0 \t\n" \\r
+ " beq SkipContextSwitch \t\n" \\r
+ " bl vTaskSwitchContext \t\n" \\r
+ "SkipContextSwitch: \t\n"\r
+ );\r
\r
/* Ready for the next interrupt. */\r
T0_IR = portTIMER_MATCH_ISR_BIT;\r
VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
- \r
+\r
/* Restore the context of the new task. */\r
portRESTORE_CONTEXT();\r
}\r
\r
void vPortDisableInterruptsFromThumb( void )\r
{\r
- __asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
- \r
+\r
void vPortEnableInterruptsFromThumb( void )\r
{\r
- __asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0} \n\t" /* Pop R0. */\r
"BX R14" ); /* Return back to thumb. */\r
}\r
void vPortEnterCritical( void )\r
{\r
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
- __asm volatile ( \r
+ __asm volatile (\r
"STMDB SP!, {R0} \n\t" /* Push R0. */\r
"MRS R0, CPSR \n\t" /* Get CPSR. */\r
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */\r
"MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
\r
- /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
directly. Increment ulCriticalNesting to keep a count of how many times\r
portENTER_CRITICAL() has been called. */\r
ulCriticalNesting++;\r
if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
{\r
/* Enable interrupts as per portEXIT_CRITICAL(). */\r
- __asm volatile ( \r
- "STMDB SP!, {R0} \n\t" /* Push R0. */ \r
- "MRS R0, CPSR \n\t" /* Get CPSR. */ \r
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \r
- "MSR CPSR, R0 \n\t" /* Write back modified value. */ \r
+ __asm volatile (\r
+ "STMDB SP!, {R0} \n\t" /* Push R0. */\r
+ "MRS R0, CPSR \n\t" /* Get CPSR. */\r
+ "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */\r
+ "MSR CPSR, R0 \n\t" /* Write back modified value. */\r
"LDMIA SP!, {R0}" ); /* Pop R0. */\r
}\r
}\r
projects / freertos / blobdiff