/*\r
- FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.0.0\r
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software. If you wish to use our Amazon\r
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/* Standard includes. */\r
#include <stdlib.h>\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
- __asm volatile ( "CPSID i" ); \\r
+ __asm volatile ( "CPSID i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
- __asm volatile ( "CPSIE i" ); \\r
+ __asm volatile ( "CPSIE i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
{ \\r
portCPU_IRQ_DISABLE(); \\r
portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
- __asm( "DSB \n" \\r
- "ISB \n" ); \\r
+ __asm volatile ( "DSB \n" \\r
+ "ISB \n" ); \\r
portCPU_IRQ_ENABLE(); \\r
}\r
\r
#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )\r
#define portBIT_0_SET ( ( uint8_t ) 0x01 )\r
\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/* The space on the stack required to hold the FPU registers. This is 32 64-bit\r
+registers, plus a 32-bit status register. */\r
+#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
*/\r
extern void vPortRestoreTaskContext( void );\r
\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*\r
+ * If the application provides an implementation of vApplicationIRQHandler(),\r
+ * then it will get called directly without saving the FPU registers on\r
+ * interrupt entry, and this weak implementation of\r
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\r
+ * it should never actually get called so its implementation contains a\r
+ * call to configASSERT() that will always fail.\r
+ *\r
+ * If the application provides its own implementation of\r
+ * vApplicationFPUSafeIRQHandler() then the implementation of\r
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers\r
+ * before calling it.\r
+ *\r
+ * Therefore, if the application writer wants FPU registers to be saved on\r
+ * interrupt entry their IRQ handler must be called\r
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\r
+ * FPU registers to be saved on interrupt entry their IRQ handler must be\r
+ * called vApplicationIRQHandler().\r
+ */\r
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/* A variable is used to keep track of the critical section nesting. This\r
\r
/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then\r
a floating point context must be saved and restored for the task. */\r
-uint32_t ulPortTaskHasFPUContext = pdFALSE;\r
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;\r
\r
/* Set to 1 to pend a context switch from an ISR. */\r
-uint32_t ulPortYieldRequired = pdFALSE;\r
+volatile uint32_t ulPortYieldRequired = pdFALSE;\r
\r
/* Counts the interrupt nesting depth. A context switch is only performed if\r
if the nesting depth is 0. */\r
-uint32_t ulPortInterruptNesting = 0UL;\r
+volatile uint32_t ulPortInterruptNesting = 0UL;\r
\r
+/* Used in the asm file. */\r
__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\r
__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\r
__attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;\r
pxTopOfStack--;\r
\r
/* Next all the registers other than the stack pointer. */\r
- *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */\r
pxTopOfStack--;\r
*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */\r
pxTopOfStack--;\r
/* The task will start with a critical nesting count of 0 as interrupts are\r
enabled. */\r
*pxTopOfStack = portNO_CRITICAL_NESTING;\r
- pxTopOfStack--;\r
\r
- /* The task will start without a floating point context. A task that uses\r
- the floating point hardware must call vPortTaskUsesFPU() before executing\r
- any floating point instructions. */\r
- *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+ #if( configUSE_TASK_FPU_SUPPORT == 1 )\r
+ {\r
+ /* The task will start without a floating point context. A task that\r
+ uses the floating point hardware must call vPortTaskUsesFPU() before\r
+ executing any floating point instructions. */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+ }\r
+ #elif( configUSE_TASK_FPU_SUPPORT == 2 )\r
+ {\r
+ /* The task will start with a floating point context. Leave enough\r
+ space for the registers - and ensure they are initialised to 0. */\r
+ pxTopOfStack -= portFPU_REGISTER_WORDS;\r
+ memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = pdTRUE;\r
+ ulPortTaskHasFPUContext = pdTRUE;\r
+ }\r
+ #else\r
+ {\r
+ #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\r
+ }\r
+ #endif\r
\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( ulPortInterruptNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
BaseType_t xPortStartScheduler( void )\r
{\r
uint32_t ulAPSR;\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
}\r
}\r
\r
- /* Will only get here if xTaskStartScheduler() was called with the CPU in\r
+ /* Will only get here if vTaskStartScheduler() was called with the CPU in\r
a non-privileged mode or the binary point register was not set to its lowest\r
- possible value. */\r
+ possible value. prvTaskExitError() is referenced to prevent a compiler\r
+ warning about it being defined but not referenced in the case that the user\r
+ defines their own exit address. */\r
+ ( void ) prvTaskExitError;\r
return 0;\r
}\r
/*-----------------------------------------------------------*/\r
directly. Increment ulCriticalNesting to keep a count of how many times\r
portENTER_CRITICAL() has been called. */\r
ulCriticalNesting++;\r
+\r
+ /* This is not the interrupt safe version of the enter critical function so\r
+ assert() if it is being called from an interrupt context. Only API\r
+ functions that end in "FromISR" can be used in an interrupt. Only assert if\r
+ the critical nesting count is 1 to protect against recursive calls if the\r
+ assert function also uses a critical section. */\r
+ if( ulCriticalNesting == 1 )\r
+ {\r
+ configASSERT( ulPortInterruptNesting == 0 );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
updated. */\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
- __asm( "dsb \n"\r
- "isb \n" );\r
+ __asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortTaskUsesFPU( void )\r
-{\r
-uint32_t ulInitialFPSCR = 0;\r
+#if( configUSE_TASK_FPU_SUPPORT != 2 )\r
\r
- /* A task is registering the fact that it needs an FPU context. Set the\r
- FPU flag (which is saved as part of the task context). */\r
- ulPortTaskHasFPUContext = pdTRUE;\r
+ void vPortTaskUsesFPU( void )\r
+ {\r
+ uint32_t ulInitialFPSCR = 0;\r
\r
- /* Initialise the floating point status register. */\r
- __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
-}\r
+ /* A task is registering the fact that it needs an FPU context. Set the\r
+ FPU flag (which is saved as part of the task context). */\r
+ ulPortTaskHasFPUContext = pdTRUE;\r
+\r
+ /* Initialise the floating point status register. */\r
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
+ }\r
+\r
+#endif /* configUSE_TASK_FPU_SUPPORT */\r
/*-----------------------------------------------------------*/\r
\r
void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
{\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
- __asm( "dsb \n"\r
- "isb \n" );\r
+ __asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
}\r
portCPU_IRQ_ENABLE();\r
\r
configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
\r
FreeRTOS maintains separate thread and ISR API functions to ensure\r
- interrupt entry is as fast and simple as possible.\r
-\r
- The following links provide detailed information:\r
- http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
- http://www.freertos.org/FAQHelp.html */\r
+ interrupt entry is as fast and simple as possible. */\r
configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
\r
/* Priority grouping: The interrupt controller (GIC) allows the bits\r
#endif /* configASSERT_DEFINED */\r
/*-----------------------------------------------------------*/\r
\r
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )\r
+{\r
+ ( void ) ulICCIAR;\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
projects / freertos / blobdiff