/*\r
- FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and\r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety\r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting,\r
- licensing and training services.\r
-*/\r
-\r
-\r
- .org 0\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
.text\r
+ .arm\r
\r
.set SYS_MODE, 0x1f\r
.set SVC_MODE, 0x13\r
.set IRQ_MODE, 0x12\r
\r
- .extern _boot\r
- .extern vTaskSwitchContext\r
+ /* Hardware registers. */\r
.extern ulICCIAR\r
.extern ulICCEOIR\r
+ .extern ulICCPMR\r
+\r
+ /* Variables and functions. */\r
+ .extern ulMaxAPIPriorityMask\r
+ .extern _freertos_vector_table\r
+ .extern pxCurrentTCB\r
+ .extern vTaskSwitchContext\r
+ .extern vApplicationIRQHandler\r
+ .extern ulPortInterruptNesting\r
+ .extern ulPortTaskHasFPUContext\r
\r
- .global _vector_table\r
- .global FIQInterrupt\r
- .global Undefined\r
- .global PrefetchAbortHandler\r
- .global DataAbortInterrupt\r
.global FreeRTOS_IRQ_Handler\r
.global FreeRTOS_SWI_Handler\r
+ .global vPortRestoreTaskContext\r
+\r
+\r
+\r
+\r
+.macro portSAVE_CONTEXT\r
+\r
+ /* Save the LR and SPSR onto the system mode stack before switching to\r
+ system mode to save the remaining system mode registers. */\r
+ SRSDB sp!, #SYS_MODE\r
+ CPS #SYS_MODE\r
+ PUSH {R0-R12, R14}\r
+\r
+ /* Push the critical nesting count. */\r
+ LDR R2, ulCriticalNestingConst\r
+ LDR R1, [R2]\r
+ PUSH {R1}\r
+\r
+ /* Does the task have a floating point context that needs saving? If\r
+ ulPortTaskHasFPUContext is 0 then no. */\r
+ LDR R2, ulPortTaskHasFPUContextConst\r
+ LDR R3, [R2]\r
+ CMP R3, #0\r
+\r
+ /* Save the floating point context, if any. */\r
+ FMRXNE R1, FPSCR\r
+ VPUSHNE {D0-D15}\r
+ VPUSHNE {D16-D31}\r
+ PUSHNE {R1}\r
+\r
+ /* Save ulPortTaskHasFPUContext itself. */\r
+ PUSH {R3}\r
+\r
+ /* Save the stack pointer in the TCB. */\r
+ LDR R0, pxCurrentTCBConst\r
+ LDR R1, [R0]\r
+ STR SP, [R1]\r
+\r
+ .endm\r
+\r
+; /**********************************************************************/\r
+\r
+.macro portRESTORE_CONTEXT\r
+\r
+ /* Set the SP to point to the stack of the task being restored. */\r
+ LDR R0, pxCurrentTCBConst\r
+ LDR R1, [R0]\r
+ LDR SP, [R1]\r
+\r
+ /* Is there a floating point context to restore? If the restored\r
+ ulPortTaskHasFPUContext is zero then no. */\r
+ LDR R0, ulPortTaskHasFPUContextConst\r
+ POP {R1}\r
+ STR R1, [R0]\r
+ CMP R1, #0\r
+\r
+ /* Restore the floating point context, if any. */\r
+ POPNE {R0}\r
+ VPOPNE {D16-D31}\r
+ VPOPNE {D0-D15}\r
+ VMSRNE FPSCR, R0\r
+\r
+ /* Restore the critical section nesting depth. */\r
+ LDR R0, ulCriticalNestingConst\r
+ POP {R1}\r
+ STR R1, [R0]\r
+\r
+ /* Ensure the priority mask is correct for the critical nesting depth. */\r
+ LDR R2, ulICCPMRConst\r
+ LDR R2, [R2]\r
+ CMP R1, #0\r
+ MOVEQ R4, #255\r
+ LDRNE R4, ulMaxAPIPriorityMaskConst\r
+ LDRNE R4, [R4]\r
+ STR R4, [R2]\r
+\r
+ /* Restore all system mode registers other than the SP (which is already\r
+ being used). */\r
+ POP {R0-R12, R14}\r
+\r
+ /* Return to the task code, loading CPSR on the way. */\r
+ RFEIA sp!\r
+\r
+ .endm\r
\r
- .section .vectors\r
\r
-_vector_table:\r
- B _boot\r
- B Undefined\r
- ldr pc, _swi\r
- B PrefetchAbortHandler\r
- B DataAbortHandler\r
- NOP /* Placeholder for address exception vector*/\r
- LDR PC, _irq\r
- B FIQHandler\r
\r
-_irq: .word FreeRTOS_IRQ_Handler\r
-_swi: .word FreeRTOS_SWI_Handler\r
\r
/******************************************************************************\r
- * SVC handler is used to start the scheduler and yield a task.\r
+ * SVC handler is used to start the scheduler.\r
*****************************************************************************/\r
+.align 4\r
+.type FreeRTOS_SWI_Handler, %function\r
FreeRTOS_SWI_Handler:\r
-\r
/* Save the context of the current task and select a new task to run. */\r
-// portSAVE_CONTEXT\r
- LDR R0, =vTaskSwitchContext\r
+ portSAVE_CONTEXT\r
+ LDR R0, vTaskSwitchContextConst\r
BLX R0\r
+ portRESTORE_CONTEXT\r
+\r
\r
+/******************************************************************************\r
+ * vPortRestoreTaskContext is used to start the scheduler.\r
+ *****************************************************************************/\r
+.type vPortRestoreTaskContext, %function\r
vPortRestoreTaskContext:\r
-// portRESTORE_CONTEXT\r
+ /* Switch to system mode. */\r
+ CPS #SYS_MODE\r
+ portRESTORE_CONTEXT\r
\r
+.align 4\r
+.type FreeRTOS_IRQ_Handler, %function\r
FreeRTOS_IRQ_Handler:\r
/* Return to the interrupted instruction. */\r
SUB lr, lr, #4\r
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting\r
for future use. r1 holds the original ulPortInterruptNesting value for\r
future use. */\r
- LDR r3, =ulPortInterruptNesting\r
+ LDR r3, ulPortInterruptNestingConst\r
LDR r1, [r3]\r
ADD r4, r1, #1\r
STR r4, [r3]\r
/* Read value from the interrupt acknowledge register, which is stored in r0\r
for future parameter and interrupt clearing use. */\r
LDR r2, ulICCIARConst\r
+ LDR r2, [r2]\r
LDR r0, [r2]\r
\r
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for\r
- future use. */\r
+ future use. _RB_ Does this ever actually need to be done provided the start\r
+ of the stack is 8-byte aligned? */\r
MOV r2, sp\r
AND r2, r2, #4\r
SUB sp, sp, r2\r
\r
- /* Call the interrupt handler. */\r
- PUSH {r0-r3, lr}\r
- BL vApplicationIRQHandler\r
- POP {r0-r3, lr}\r
+ /* Call the interrupt handler. r4 pushed to maintain alignment. */\r
+ PUSH {r0-r4, lr}\r
+ LDR r1, vApplicationIRQHandlerConst\r
+ BLX r1\r
+ POP {r0-r4, lr}\r
ADD sp, sp, r2\r
\r
CPSID i\r
+ DSB\r
+ ISB\r
\r
/* Write the value read from ICCIAR to ICCEOIR. */\r
LDR r4, ulICCEOIRConst\r
+ LDR r4, [r4]\r
STR r0, [r4]\r
\r
/* Restore the old nesting count. */\r
POP {LR}\r
MSR SPSR_cxsf, LR\r
POP {LR}\r
-// portSAVE_CONTEXT\r
+ portSAVE_CONTEXT\r
\r
/* Call the function that selects the new task to execute.\r
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\r
instructions, or 8 byte aligned stack allocated data. LR does not need\r
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\r
- BL vTaskSwitchContext\r
+ LDR R0, vTaskSwitchContextConst\r
+ BLX R0\r
\r
/* Restore the context of, and branch to, the task selected to execute\r
next. */\r
-// portRESTORE_CONTEXT\r
+ portRESTORE_CONTEXT\r
\r
-ulICCIARConst: .word ulICCIAR\r
-ulICCEOIRConst: .word ulICCEOIR\r
\r
+/******************************************************************************\r
+ * If the application provides an implementation of vApplicationIRQHandler(),\r
+ * then it will get called directly without saving the FPU registers on\r
+ * interrupt entry, and this weak implementation of\r
+ * vApplicationIRQHandler() will not get called.\r
+ *\r
+ * If the application provides its own implementation of\r
+ * vApplicationFPUSafeIRQHandler() then this implementation of\r
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then\r
+ * call vApplicationFPUSafeIRQHandler().\r
+ *\r
+ * Therefore, if the application writer wants FPU registers to be saved on\r
+ * interrupt entry their IRQ handler must be called\r
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\r
+ * FPU registers to be saved on interrupt entry their IRQ handler must be\r
+ * called vApplicationIRQHandler().\r
+ *****************************************************************************/\r
\r
-Undefined:\r
- B .\r
+.align 4\r
+.weak vApplicationIRQHandler\r
+.type vApplicationIRQHandler, %function\r
+vApplicationIRQHandler:\r
+ PUSH {LR}\r
+ FMRX R1, FPSCR\r
+ VPUSH {D0-D15}\r
+ VPUSH {D16-D31}\r
+ PUSH {R1}\r
\r
-PrefetchAbortHandler:\r
- B .\r
+ LDR r1, vApplicationFPUSafeIRQHandlerConst\r
+ BLX r1\r
\r
-FIQHandler:\r
- B .\r
+ POP {R0}\r
+ VPOP {D16-D31}\r
+ VPOP {D0-D15}\r
+ VMSR FPSCR, R0\r
\r
-DataAbortHandler:\r
- B .\r
+ POP {PC}\r
+\r
+\r
+ulICCIARConst: .word ulICCIAR\r
+ulICCEOIRConst: .word ulICCEOIR\r
+ulICCPMRConst: .word ulICCPMR\r
+pxCurrentTCBConst: .word pxCurrentTCB\r
+ulCriticalNestingConst: .word ulCriticalNesting\r
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext\r
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask\r
+vTaskSwitchContextConst: .word vTaskSwitchContext\r
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler\r
+ulPortInterruptNestingConst: .word ulPortInterruptNesting\r
+vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler\r
\r
.end\r
\r
projects / freertos / blobdiff