/*\r
- FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
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-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
+ * FreeRTOS Kernel V10.3.0\r
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
\r
/*-----------------------------------------------------------\r
* Implementation of functions defined in portable.h for the ARM CM0 port.\r
#include "task.h"\r
\r
/* Constants required to manipulate the NVIC. */\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t *) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t *) 0xe000e014 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK 0x00000004\r
-#define portNVIC_SYSTICK_INT 0x00000002\r
-#define portNVIC_SYSTICK_ENABLE 0x00000001\r
-#define portNVIC_PENDSVSET 0x10000000\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )\r
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )\r
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )\r
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
\r
+/* The systick is a 24-bit counter. */\r
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )\r
+\r
+/* A fiddle factor to estimate the number of SysTick counts that would have\r
+occurred while the SysTick counter is stopped during tickless idle\r
+calculations. */\r
+#ifndef portMISSED_COUNTS_FACTOR\r
+ #define portMISSED_COUNTS_FACTOR ( 45UL )\r
+#endif\r
+\r
/* Let the user override the pre-loading of the initial LR with the address of\r
-prvTaskExitError() in case is messes up unwinding of the stack in the\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
debugger. */\r
#ifdef configTASK_RETURN_ADDRESS\r
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
-/* Each task maintains its own interrupt status in the critical nesting\r
-variable. */\r
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
-\r
/*\r
- * Setup the timer to generate the tick interrupts.\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
*/\r
-static void prvSetupTimerInterrupt( void );\r
+void vPortSetupTimerInterrupt( void );\r
\r
/*\r
* Exception handlers.\r
\r
/*-----------------------------------------------------------*/\r
\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+* The number of SysTick increments that make up one tick period.\r
+*/\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulTimerCountsForOneTick = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * The maximum number of tick periods that can be suppressed is limited by the\r
+ * 24 bit resolution of the SysTick timer.\r
+ */\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*\r
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
+ * power functionality only.\r
+ */\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+ static uint32_t ulStoppedTimerCompensation = 0;\r
+#endif /* configUSE_TICKLESS_IDLE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
/*\r
* See header file for description.\r
*/\r
\r
static void prvTaskExitError( void )\r
{\r
+volatile uint32_t ulDummy = 0UL;\r
+\r
/* A function that implements a task must not exit or attempt to return to\r
its caller as there is nothing to return to. If a task wants to exit it\r
should instead call vTaskDelete( NULL ).\r
defined, then stop here so application writers can catch the error. */\r
configASSERT( uxCriticalNesting == ~0UL );\r
portDISABLE_INTERRUPTS();\r
- for( ;; );\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ started to remove a compiler warning about the function being defined\r
+ but never called. ulDummy is used purely to quieten other warnings\r
+ about code appearing after this function is called - making ulDummy\r
+ volatile makes the compiler think the function could return and\r
+ therefore not output an 'unreachable code' warning for code that appears\r
+ after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
table offset register that can be used to locate the initial stack value.\r
Not all M0 parts have the application vector table at address 0. */\r
__asm volatile(\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Obtain location of pxCurrentTCB. */\r
- " ldr r3, [r2] \n"\r
- " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
- " add r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " .syntax unified \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Obtain location of pxCurrentTCB. */\r
+ " ldr r3, [r2] \n"\r
+ " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
" movs r0, #2 \n" /* Switch to the psp stack. */\r
- " msr CONTROL, r0 \n"\r
- " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */\r
- " mov lr, r5 \n" /* lr is now in r5. */\r
+ " msr CONTROL, r0 \n"\r
+ " isb \n"\r
+ " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */\r
+ " mov lr, r5 \n" /* lr is now in r5. */\r
+ " pop {r3} \n" /* Return address is now in r3. */\r
+ " pop {r2} \n" /* Pop and discard XPSR. */\r
" cpsie i \n" /* The first task has its context and interrupts can be enabled. */\r
- " pop {pc} \n" /* Finally, pop the PC to jump to the user defined task code. */\r
+ " bx r3 \n" /* Finally, jump to the user defined task code. */\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB "\r
);\r
}\r
*/\r
BaseType_t xPortStartScheduler( void )\r
{\r
- /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
- *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
- *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
- prvSetupTimerInterrupt();\r
+ vPortSetupTimerInterrupt();\r
\r
/* Initialise the critical nesting count ready for the first task. */\r
uxCriticalNesting = 0;\r
/* Should never get here as the tasks will now be executing! Call the task\r
exit error function to prevent compiler warnings about a static function\r
not being called in the case that the application writer overrides this\r
- functionality by defining configTASK_RETURN_ADDRESS. */\r
+ functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ vTaskSwitchContext() so link time optimisation does not remove the\r
+ symbol. */\r
+ vTaskSwitchContext();\r
prvTaskExitError();\r
\r
/* Should not get here! */\r
void vPortYield( void )\r
{\r
/* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
\r
/* Barriers are normally not required but do ensure the code is completely\r
within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void )\r
{\r
- portDISABLE_INTERRUPTS();\r
- uxCriticalNesting++;\r
- __asm volatile( "dsb" );\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
void vPortExitCritical( void )\r
{\r
configASSERT( uxCriticalNesting );\r
- uxCriticalNesting--;\r
- if( uxCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
" mrs r0, PRIMASK \n"\r
" cpsid i \n"\r
" bx lr "\r
+ ::: "memory"\r
);\r
-\r
- /* To avoid compiler warnings. This line will never be reached. */\r
- return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vClearInterruptMaskFromISR( uint32_t ulMask )\r
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )\r
{\r
__asm volatile(\r
" msr PRIMASK, r0 \n"\r
" bx lr "\r
+ ::: "memory"\r
);\r
-\r
- /* Just to avoid compiler warning. */\r
- ( void ) ulMask;\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
__asm volatile\r
(\r
+ " .syntax unified \n"\r
" mrs r0, psp \n"\r
" \n"\r
" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
" ldr r2, [r3] \n"\r
" \n"\r
- " sub r0, r0, #32 \n" /* Make space for the remaining low registers. */\r
+ " subs r0, r0, #32 \n" /* Make space for the remaining low registers. */\r
" str r0, [r2] \n" /* Save the new top of stack. */\r
" stmia r0!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */\r
" mov r4, r8 \n" /* Store the high registers. */\r
" mov r5, r9 \n"\r
" mov r6, r10 \n"\r
" mov r7, r11 \n"\r
- " stmia r0!, {r4-r7} \n"\r
+ " stmia r0!, {r4-r7} \n"\r
" \n"\r
" push {r3, r14} \n"\r
" cpsid i \n"\r
" \n"\r
" ldr r1, [r2] \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
- " add r0, r0, #16 \n" /* Move to the high registers. */\r
+ " adds r0, r0, #16 \n" /* Move to the high registers. */\r
" ldmia r0!, {r4-r7} \n" /* Pop the high registers. */\r
" mov r8, r4 \n"\r
" mov r9, r5 \n"\r
" \n"\r
" msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
" \n"\r
- " sub r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */\r
- " ldmia r0!, {r4-r7} \n" /* Pop low registers. */\r
+ " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */\r
+ " ldmia r0!, {r4-r7} \n" /* Pop low registers. */\r
" \n"\r
" bx r3 \n"\r
" \n"\r
- " .align 2 \n"\r
+ " .align 4 \n"\r
"pxCurrentTCBConst: .word pxCurrentTCB "\r
);\r
}\r
if( xTaskIncrementTick() != pdFALSE )\r
{\r
/* Pend a context switch. */\r
- *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
}\r
}\r
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
* Setup the systick timer to generate the tick interrupts at the required\r
* frequency.\r
*/\r
-void prvSetupTimerInterrupt( void )\r
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
{\r
+ /* Calculate the constants required to configure the tick interrupt. */\r
+ #if( configUSE_TICKLESS_IDLE == 1 )\r
+ {\r
+ ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );\r
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;\r
+ }\r
+ #endif /* configUSE_TICKLESS_IDLE */\r
+\r
+ /* Stop and reset the SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG = 0UL;\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
/* Configure SysTick to interrupt at the requested rate. */\r
- *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
}\r
/*-----------------------------------------------------------*/\r
\r
+#if( configUSE_TICKLESS_IDLE == 1 )\r
+\r
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+ {\r
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
+ TickType_t xModifiableIdleTime;\r
+\r
+ /* Make sure the SysTick reload value does not overflow the counter. */\r
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
+ {\r
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
+ }\r
+\r
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for\r
+ is accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. */\r
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime\r
+ tick periods. -1 is used because this code will execute part way\r
+ through one of the tick periods. */\r
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
+ method as that will mask interrupts that should exit sleep mode. */\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* If a context switch is pending or a task is waiting for the scheduler\r
+ to be unsuspended then abandon the low power entry. */\r
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
+ {\r
+ /* Restart from whatever is left in the count register to complete\r
+ this tick period. */\r
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Reset the reload register to the value required for normal tick\r
+ periods. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+ }\r
+ else\r
+ {\r
+ /* Set the new reload value. */\r
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
+\r
+ /* Clear the SysTick count flag and set the count value back to\r
+ zero. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+\r
+ /* Restart SysTick. */\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+\r
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
+ set its parameter to 0 to indicate that its implementation contains\r
+ its own wait for interrupt or wait for event instruction, and so wfi\r
+ should not be executed again. However, the original expected idle\r
+ time variable must remain unmodified, so a copy is taken. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "wfi" );\r
+ __asm volatile( "isb" );\r
+ }\r
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
+\r
+ /* Re-enable interrupts to allow the interrupt that brought the MCU\r
+ out of sleep mode to execute immediately. see comments above\r
+ __disable_interrupt() call above. */\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* Disable interrupts again because the clock is about to be stopped\r
+ and interrupts that execute while the clock is stopped will increase\r
+ any slippage between the time maintained by the RTOS and calendar\r
+ time. */\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,\r
+ the time the SysTick is stopped for is accounted for as best it can\r
+ be, but using the tickless mode will inevitably result in some tiny\r
+ drift of the time maintained by the kernel with respect to calendar\r
+ time*/\r
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
+\r
+ /* Determine if the SysTick clock has already counted to zero and\r
+ been set back to the current reload value (the reload back being\r
+ correct for the entire expected idle time) or if the SysTick is yet\r
+ to count to zero (in which case an interrupt other than the SysTick\r
+ must have brought the system out of sleep mode). */\r
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
+ {\r
+ uint32_t ulCalculatedLoadValue;\r
+\r
+ /* The tick interrupt is already pending, and the SysTick count\r
+ reloaded with ulReloadValue. Reset the\r
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
+ period. */\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
+\r
+ /* Don't allow a tiny value, or values that have somehow\r
+ underflowed because the post sleep hook did something\r
+ that took too long. */\r
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
+ {\r
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
+ }\r
+\r
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
+\r
+ /* As the pending tick will be processed as soon as this\r
+ function exits, the tick value maintained by the tick is stepped\r
+ forward by one less than the time spent waiting. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep.\r
+ Work out how long the sleep lasted rounded to complete tick\r
+ periods (not the ulReload value which accounted for part\r
+ ticks). */\r
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
+\r
+ /* How many complete tick periods passed while the processor\r
+ was waiting? */\r
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
+ }\r
+\r
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
+ value. */\r
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
+\r
+ /* Exit with interrpts enabled. */\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+ }\r
+ }\r
+\r
+#endif /* configUSE_TICKLESS_IDLE */\r
projects / freertos / blobdiff